EP-4121864-B1 - METHOD TO OVERLOAD HARDWARE PIN FOR IMPROVED SYSTEM MANAGEMENT

Inventors

• LADKANI, NEERAJ
• BULUSU, MALLIK
• DHARIA, Sagar
• AHMED, MUHAMMAD ASHFAQ

Dates

Publication Date

20260513

Application Date

20210303

Claims (10)

1. A baseboard management controller, BMC (108), comprising: a connector (112) that facilitates electronic communication between the BMC and a hardware interrupt pin (110) of a host processor (102); a BMC processor (126); BMC firmware (124) in electronic communication with the BMC processor, wherein the BMC firmware defines context information and triggering events for a plurality of sets of instructions that are included in an interrupt handler in host firmware, and wherein the BMC firmware comprises instructions that are executable by the BMC processor to: generate an interrupt signal on the hardware interrupt pin; and provide the context information that corresponds to a triggering event to the host processor.
2. The BMC of claim 1, wherein: the BMC firmware further comprises additional instructions that are executable by the BMC processor to detect occurrence of the triggering event; and the interrupt signal is generated and the context information is provided to the host processor in response to detecting the occurrence of the triggering event.
3. The BMC of claim 1, wherein providing the context information to the host processor comprises writing the context information to a memory location (120) that is shared by the BMC and the host processor and that is accessible via a data communication interface.
4. The BMC of claim 1, wherein providing the context information to the host processor comprises writing the context information to a memory location that is native to the host processor and that is accessible to the BMC via a data communication interface.
5. A computer system, comprising: a host processor (102) comprising a hardware interrupt pin (110); host firmware (106) comprising an interrupt handler (116), wherein the interrupt handler comprises a plurality of sets of instructions that are executable by the host processor; and the BMC of one of claims 1 to 4.
6. The computer system of claim 5, wherein the interrupt handler is configured so that: the host processor executes the set of instructions identified by the context information in response to the interrupt signal; and the host processor does not execute other sets of instructions in the interrupt handler in response to the interrupt signal.
7. The computer system of claim 5, wherein the host processor obtains the context information via an input/output read instruction that is native to the host processor.
8. The computer system of claim 5, wherein the BMC is additionally configured to provide a code segment to the host processor along with the context information.
9. The computer system of claim 5, wherein: each of the plurality of sets of instructions in the interrupt handler is associated with an identifier; and the context information comprises the identifier that is associated with the set of instructions that should be executed.
10. The computer system of claim 5, wherein: each of the plurality of sets of instructions in the interrupt handler is associated with an identifier; and each identifier that is associated with a particular set of instructions in the interrupt handler is associated with a triggering event in the BMC firmware.

Description

BACKGROUND Cloud computing is the delivery of computing services (e.g., servers, storage, databases, networking, software, analytics) over the Internet. Broadly speaking, a cloud computing system includes two sections, a front end and a back end, that are in communication with one another via the Internet. The front end includes the interface that users encounter through a client device. The back end includes the resources that deliver cloud-computing services, including processors, memory, storage, and networking hardware. The back end of a cloud computing system typically includes one or more datacenters, which may be located in different geographical areas. Each datacenter typically includes a large number (e.g., hundreds or thousands) of servers. These servers may be referred to as host computing devices. Each host computing device can be used to run one or more virtual machines. In this context, the term "host computing device" refers to a physical computer system, while the term "virtual machine" refers to an emulation of a computer system on a host computing device. Host computing devices in a cloud computing system can be configured with at least two distinct layers: a system layer and a management layer. The system layer includes system firmware (e.g., Unified Extensible Firmware Interface (UEFI), Basic Input/Output System (BIOS)), device firmware, an operating system, a hypervisor, virtual machines, and so forth. The management layer can include an auxiliary service processor such as a baseboard management controller (BMC), as well as a rack/chassis level management software stack that in turn works with the BMC. The BMC is a specialized microcontroller that can be embedded on the motherboard of a host computing device. It can be useful for BMCs to be included in host computing devices within a cloud computing system because they allow system administrators to perform various tasks remotely. For example, a system administrator can remotely communicate with a BMC to take corrective actions, such as resetting or power cycling a host computing device. Under some circumstances, the components within the system layer of a host computing device and the components within the management layer of a host computing device can work together. For example, hardware errors detected by the BMC can be communicated to the system firmware and/or the operating system for the purposes of graceful error handling, error containment, field-replaceable unit (FRU) isolation and logging, etc. As another example, the BMC can be responsible for actively monitoring battery events and communicating them to the operating system via the system firmware. Communication between system layer components and management layer components can be made possible by provisions in the hardware of a host computing device. For example, one or more of the digital signal pins (e.g., general-purpose input/output (GPIO) pins) on the host processor can be reserved for interrupt signals from the BMC. A digital signal pin that is reserved for an interrupt signal from the BMC may be referred to herein as a hardware interrupt pin. A hardware interrupt pin can be dedicated to a particular function. When the BMC generates an interrupt signal on a hardware interrupt pin (e.g., by changing the state of the hardware interrupt pin from low to high or vice versa), the host processor can perform the function that is associated with that particular hardware interrupt pin (e.g., communicating certain information to the system firmware and/or the operating system). Unfortunately, current approaches require hardware interrupt pins to be reserved during hardware design in order to implement a particular function. This provides limited flexibility. For example, suppose that a host computing device is designed such that the host processor includes only one hardware interrupt pin. With current approaches, this means that only one function involving the BMC and the host processor can be implemented. Even if a host computing device is designed such that the host processor includes a plurality of hardware interrupt pins, the number of functions involving the BMC and the host processor is still quite limited. In general, if a host computing device is designed such that the host processor includes N hardware interrupt pins (where N is a positive integer), this means that only N different functions involving the BMC and the host processor can be implemented with current approaches. However, after the hardware for the host computing device has been designed, users (e.g., system administrators) might think of additional functions involving the BMC and the host processor that would be useful to implement. Users might also want to change at least some functions involving the BMC and the host processor from time to time. Benefits may therefore be realized by techniques that enable greater flexibility in connection with the types and varieties of functions that can be implemented i