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EP-4128338-B1 - INTEGRATED DEVICE COMPRISING TRANSISTOR COUPLED TO A DUMMY GATE CONTACT

EP4128338B1EP 4128338 B1EP4128338 B1EP 4128338B1EP-4128338-B1

Inventors

  • YANG, HAINING
  • LI, XIA
  • YANG, BIN

Dates

Publication Date
20260513
Application Date
20210322

Claims (15)

  1. An integrated device (1600) comprising: a substrate (102, 202, 1620); a first transistor (301, 501, 601, 701, 801, 901, 1001, 1101) located over the substrate (102, 202, 1620), wherein the first transistor (301, 501, 601, 701, 801, 901, 1001, 1101) comprises a gate (110, 210, 1510); a second transistor (302, 502, 602, 702, 802, 902, 1002, 1102) located over the substrate (102, 202, 1620), wherein the second transistor (302, 502, 602, 702, 802, 902, 1002, 1102) comprises the gate (110, 210, 1510); a first gate contact coupled to the gate (110, 210, 1510) of the first transistor (301, 501, 601, 701, 801, 901, 1001, 1101) and the second transistor (302, 502, 602, 702, 802, 902, 1002, 1102), wherein the first gate contact is configured to be electrically coupled to an interconnect (260, 270, 270b, 270d-j, 270n, 270p, 1570, 1640, 1664) of the integrated device (1600); and a second gate contact coupled to the gate (110, 210, 1510) of the first transistor (301, 501, 601, 701, 801, 901, 1001, 1101) and the second transistor (302, 502, 602, 702, 802, 902, 1002, 1102), wherein the second gate contact is directly electrically coupled to only the gate (110, 210, 1510).
  2. The integrated device (1600) of claim 1, further comprising a contact interconnect (260, 260a-g, 260i, 260n, 260p, 1560) coupled to the first gate contact.
  3. The integrated device (1600) of claim 2, wherein the second gate contact is configured to tune a threshold voltage required to induce a first current flow in the first transistor (301, 501, 601, 701, 801, 901, 1001, 1101) and a second current flow in the second transistor (302, 502, 602, 702, 802, 902, 1002, 1102).
  4. The integrated device (1600) of claim 3, wherein the first transistor (301, 501, 601, 701, 801, 901, 1001, 1101) includes a p-channel field effect transistor, PFET, and the second transistor (302, 502, 602, 702, 802, 902, 1002, 1102) includes a n-channel field effect transistor, NFET.
  5. The integrated device (1600) of claim 3, wherein the first transistor (301, 501, 601, 701, 801, 901, 1001, 1101) includes a n-channel field effect transistor, NFET, and the second transistor (302, 502, 602, 702, 802, 902, 1002, 1102) includes a p-channel field effect transistor, PFET.
  6. The integrated device (1600) of claim 3, wherein the first transistor (301, 501, 601, 701, 801, 901, 1001, 1101) includes a first fin and a second fin.
  7. The integrated device (1600) of claim 6, wherein the first gate contact is located over a region that includes the first fin and the second fin.
  8. The integrated device (1600) of claim 7, wherein the second gate contact is located over the region that includes the first fin and the second fin.
  9. The integrated device (1600) of claim 7, wherein the first transistor (301, 501, 601, 801, 901, 1001, 1101) includes a p-channel field effect transistor, PFET; or wherein the first transistor (301, 501, 601, 701, 801, 901, 1001, 1101) includes a n-channel field effect transistor, NFET; or wherein the second gate contact is a dummy gate contact (250a-d)
  10. The integrated device (1600) of claim 1, wherein the first transistor (301, 501, 601, 701, 801, 901, 1001, 1101) is a p-channel field effect transistor, PFET, wherein the second transistor (302, 502, 602, 702, 802, 902, 1002, 1102) is a n-channel field effect transistor, NFET, and wherein the second gate contact is located over the first transistor (301, 501, 601, 701, 801, 901, 1001, 1101).
  11. The integrated device (1600) of claim 1, wherein the first transistor (301, 501, 601, 701, 801, 901, 1001, 1101) is a p-channel field effect transistor, PFET, wherein the second transistor (302, 502, 602, 702, 802, 902, 1002, 1102) is a n-channel field effect transistor, NFET, and wherein the second gate contact is located over the second transistor (302, 502, 602, 702, 802, 902, 1002, 1102).
  12. The integrated device (1600) of claim 1, wherein the first transistor (301, 501, 601, 701, 801, 901, 1001, 1101) is a n-channel field effect transistor, NFET, and wherein the second transistor (302, 502, 602, 702, 802, 902, 1002, 1102) is a p-channel field effect transistor, PFET; preferably wherein the second gate contact is located over the first transistor (301, 501, 601, 701, 801, 901, 1001, 1101) or the second transistor (302, 502, 602, 702, 802, 902, 1002, 1102).
  13. The integrated device (1600) of claim 1, wherein the first transistor (301, 501, 601, 701, 801, 901, 1001, 1101) includes a planar transistor, a field effect transistor, FET, or a gate (110, 210, 1510) all around, GAA, FET.
  14. A method (1400, 1800) for fabricating an integrated device (1600), comprising: providing a substrate (102, 202, 1620); forming a first transistor (301, 501, 601, 701, 801, 901, 1001, 1101) over the substrate (102, 202, 1620), wherein the first transistor (301, 501, 601, 701, 801, 901, 1001, 1101) comprises a gate (110, 210, 1510); forming a second transistor (302, 502, 602, 702, 802, 902, 1002, 1102) over the substrate (102, 202, 1620), wherein the second transistor (302, 502, 602, 702, 802, 902, 1002, 1102) comprises the gate (110, 210, 1510); forming a first gate contact over the gate (110, 210, 1510) of the first transistor (301, 501, 601, 701, 801, 901, 1001, 1101) and the second transistor (302, 502, 602, 702, 802, 902, 1002, 1102), wherein the first gate contact is configured to be electrically coupled to an interconnect (260, 270, 270b, 270d-j, 270n, 270p, 1570, 1640, 1664) of the integrated device (1600); and forming a second gate contact over the gate (110, 210, 1510), wherein the second gate contact is directly electrically coupled to only the gate (110, 210, 1510).
  15. The method (1400, 1800) of claim 14, wherein the second gate contact is configured to tune a threshold voltage required to induce a first current flow in the first transistor (301, 501, 601, 701, 801, 901, 1001, 1101) and a second current flow in the second transistor (302, 502, 602, 702, 802, 902, 1002, 1102); preferably wherein the first transistor (301, 501, 601, 701, 801, 901, 1001, 1101) includes a p-channel field effect transistor, PFET, and the second transistor (302, 502, 602, 702, 802, 902, 1002, 1102) includes a n-channel field effect transistor, NFET.

Description

Field Various features relate to transistors, but more specifically to integrated device comprising a transistor coupled to a dummy gate contact. Background FIG. 1 illustrates a planar field effect transistor (FET) 100. The FET 100 is formed over a substrate 102 and an oxide 104. The FET 100 includes a source 106, a drain 108 and a gate 110. The source 106 and the drain 108 are located over the substrate 102. When a minimum voltage is applied between the gate 110 and the substrate 102, a current may flow between the source 106 and the drain 108. There is an ongoing need to improve the performance of transistors, such as being able to better control when a current flows between a source and a drain of a transistor. WO 2017/106575 A2 discloses wafers, chips, or dies that contain fill cells with structures configured to obtain in-line data via non-contact electrical measurements ("NCEM"). Such NCEM-enabled fill cells may target/expose a variety of open-circuit, short-circuit, leakage, or excessive resistance failure modes. Such wafers, chips, or dies may include Designs of Experiments ("DOEs"), comprised of multiple NCEM-enabled fill cells, in at least two variants, all targeted to the same failure mode(s). US 2015/014781 A1 discloses a semiconductor device that has first conductivity type regions extending in a first direction, and second conductivity type regions extending in the first direction. The first conductivity type regions and the second conductivity type regions are alternately arranged in a second direction perpendicular to the first direction. The semiconductor device includes a first impurity diffused regions formed in the first conductivity type regions, a first local wiring connected to the first conductivity type regions, and extending in the second direction, a first potential supply wiring formed above the first local wiring, and extending in the first direction, and a first contact hole for connecting the first local wiring to the first potential supply wiring. US 2019/057962 A1 discloses a semiconductor structure including a substrate, dummy conductive structures, and resistor elements. The substrate includes a resistor region and has isolation structures and dummy support patterns located in the resistor region. Each of the isolation structures is located between two adjacent dummy support patterns. Each of the dummy conductive structures is disposed on each of the isolation structures and equidistant from the dummy support patterns on both sides. The resistor elements are disposed above the dummy conductive structures and aligned with the dummy conductive structures. US 2017/221821 A1 discloses a semiconductor device that includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view. US 2019/304900 A1 discloses interconnect structures that maximize integrated circuit (IC) density and corresponding formation techniques. JP 2011-146478 A discloses a semiconductor integrated circuit including an active region formed in a first region, a well region formed in a second region, transistor gate electrodes dummy gate electrodes and contacts. The active region and transistor gates form a transistor. The transistor gate electrodes and dummy gate electrodes are formed along a plurality of straight lines which are parallel with each other. The dummy gate electrodes are formed so as to be arranged in both second region and first region. The contacts are formed in the second region, and the dummy gate electrodes are electrically connected to a wiring layer having the same potential in the well region. Such a device is reducible in layout size of a region where the active region and well region are arranged, and consequently the chip size is reduced. US 2016/336183 A1 discloses At least one method, apparatus and system for processing a semiconductor wafer using a continuous active area design for manufacturing a finFET device. A first gate structure of a continuous active area design is formed in a first layer of the wafer. A first hard mask layer is deposited. A portion of the first hard mask layer is removed based upon a first trench silicide (TS) pattern and a second TS pattern. A full stripe first trench silicide (TS) structure and a second TS structure are formed. A first TS capping layer is deposited above the first TS structure and a second TS capping. The first TS capping layer is removed and a source/drain contact structure (CA) is formed above the first TS structure in a second layer of the semiconductor wafer. A gate contact structure (CB) is formed above the gate structure in the sec