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EP-4131393-B1 - DISPLAY PANEL AND DISPLAY DEVICE

EP4131393B1EP 4131393 B1EP4131393 B1EP 4131393B1EP-4131393-B1

Inventors

  • WEI, Junbo
  • YANG, Shengji
  • HUANG, KUANTA
  • LU, Pengcheng
  • TIAN, Yuanlan

Dates

Publication Date
20260506
Application Date
20200327

Claims (15)

  1. A display panel, comprising: a driving backplane (1), having a pixel driving region (S1) and a peripheral region (S2) surrounding the pixel driving region (S1), and the peripheral region (S2) being provided with bonding pads (6); an edge of the driving backplane (1) being surrounded by a first section (11) and a second section (12), and the bonding pads (6) being located between the first section (11) and the pixel driving region (S1); a plurality of detection pads (2), being disposed in the second section (12) and distributed along the second section (12); a light emitting function layer (3), being disposed on the driving backplane (1) and located in the pixel driving region (S1); a flexible circuit board (4), extending between the first section (11) and the pixel driving region (S1), and being bonded to the bonding pads (6); a first packaging layer (5), being disposed on a side of the light emitting function layer (3) away from the driving backplane (1), and an orthographic projection of the first packaging layer (5) on the driving backplane (1) covering the pixel driving region (S1) and the detection pads (2), wherein a portion of the first packaging layer (5) in the peripheral region (S2) is laminated on a surface of the detection pads (2) facing away from the driving backplane (1) to detect uniformity of the first packaging layer (5).
  2. The display panel according to claim 1, wherein the driving backplane (1) has bonding holes (100) exposing the bonding pads (6), and the flexible circuit board (4) is bonded to the bonding pads (6) through conductive material filled in the bonding holes (100).
  3. The display panel according to claim 2, wherein the driving backplane (1) comprises: a substrate (101); a driving transistor (102), being disposed on one side of the substrate (101) and located in the pixel driving region (S1); multi-layer wiring layers, being sequentially spaced and distributed on a side of the driving transistor (102) away from the substrate (101) along a direction away from the substrate (101); at least one of the wiring layers is connected to the light emitting function layer (3), and each of a gate (1023), a first pole (10211), and a second pole (10212) of the driving transistor (102) is connected to at least one of the wiring layers.
  4. The display panel according to claim 3, wherein the wiring layers comprise a first 21 wiring layer (103) and a second wiring layer (104); the driving backplane (1) further comprises: a first planarization layer (105), covering the driving transistor (102); the first wiring layer (103) is disposed on a surface of the first planarization layer (105) away from the substrate (101) and connected to the driving transistor (102); a second planarization layer (106), covering the first wiring layer (103); the second wiring layer (104) is disposed on a side of the first planarization layer (105) away from the substrate (101) and connected to the first wiring layer (103); a third planarization layer (107), covering the second wiring layer (104), and the light emitting function layer (3) is disposed on a surface of the third planarization layer (107) away from the substrate (101) and connected to the second wiring layer (104); the bonding pads (6) and the first wiring layer (103) are disposed in the same layer, and the bonding holes (100) are configured to penetrate the third planarization layer (107) and the second planarization layer (106).
  5. The display panel according to claim 4, wherein the driving transistor (102) comprises: an active layer (1021), being disposed in the substrate (101), the first pole (10211) and the second pole (10212) are disposed in the active layer (1021) at intervals; a gate insulating layer (1022), being disposed on the active layer (1021) and exposing the first pole (10211) and the second pole (10212); the gate (1023) is disposed on a surface of the gate insulating layer (1022) away from the active layer (1021); the first pole (10211), the second pole (10212) and the gate (1023) are connected to the first wiring layer (103).
  6. The display panel according to claim 1, wherein the light emitting function layer (3) comprises: a first electrode (31), being disposed on the driving backplane (1); the detection pads (2) and the first electrode (31) are disposed in the same layer; a light emitting material layer (33), being disposed on a side of the first electrode (31) away from the driving backplane (1); a second electrode (34), being disposed on a side of the light emitting material layer (33) away from the driving backplane (1).
  7. The display panel according to claim 2, wherein the flexible circuit board (4) has a plurality of conductive contact pieces (41) disposed side by side at intervals; numbers of the bonding pads (6) and the bonding holes (100) are the same and both are multiple, each of the bonding pads (6) is exposed from each of the bonding holes (100) in a one-to-one correspondence, and each of the conductive contact pieces (41) covers each of the bonding holes (100) in a one-to-one correspondence, and is connected to the bonding pads (6) through a conductive material.
  8. The display panel according to claim 7, wherein an area of a region of the conductive contact pieces (41) for connecting with the bonding pads (6) is not less than 80% of an area of the conductive contact pieces (41).
  9. The display panel according to claim 1, wherein the driving backplane (1) is in a shape of rectangle, the first section (11) is one side of the rectangle, and the second section (12) includes other sides of the rectangle; wherein edges of the driving backplane (1) include opposite first short side and second short side and opposite first long side and second long side, the first section (11) is the first short side, and the second section (12) includes a second short side, a first long side, and a second long side; the second short side, the first long side and the second long side are all provided with a same number of detection pads (2).
  10. The display panel according to claim 1, wherein an aperture of the bonding holes (100) gradually decreases toward the bonding pads (6).
  11. The display panel according to claim 10, wherein a slope of a sidewall of the bonding holes (100) with respect to the bonding pads (6) is not less than 40° and not more than 70°.
  12. The display panel according to claim 1, wherein the display panel further comprises: a color film layer (7), being disposed on a side of the first packaging layer (5) away from the driving backplane (1) and corresponding to the pixel driving region (S1); a second packaging layer (8), being disposed on a side of the color film layer (7) away from the driving backplane (1), and an orthographic projection of the second packaging layer (8) on the driving backplane (1) covers the pixel driving region (S1), the peripheral region (S2) and the detection pads (2); a transparent cover plate (9), covering at least the second packaging layer (8) and corresponding to the pixel driving region (S1).
  13. The display panel according to claim 12, wherein the first packaging layer (5) and the second packaging layer (8) are sequentially laminated on surfaces of the detection pads (2) away from the driving backplane (1) in regions corresponding to the detection pads (2).
  14. The display panel according to claim 12, wherein a projection of the color film layer (7) on the driving backplane (1) is located in the pixel driving region (S1), and a distance between the color film layer (7) and the detection pads (2) in a direction parallel to the driving backplane (1) is 150µm to 200µm.
  15. A display device comprising the display panel of any one of claims 1-14.

Description

TECHNICAL FIELD The present disclosure relates to the field of display technology, and in particular, to a display panel and a display device. BACKGROUND Micro OLED displays involve the combination of organic light emitting diode (OLED) technology and CMOS technology, and relate to the cross-integration of the optoelectronic industry and the microelectronics industry, which has promoted the development of a new generation of micro display technology. It has also promoted the research and development of organic electronics on silicon and even molecular electronics on silicon. Micro OLED displays have excellent display characteristics, such as high resolution, high brightness, rich colors, low drive voltage, fast response speed, and low power consumption, and have broad development prospects. It should be noted that the information disclosed in the above described background only serves to enhance an understanding of the background of the present disclosure, which may include information that does not constitute prior art known to those skilled in the art. US2005/236620A1 describes the provision of an organic EL device capable of making uniform a dry speed of a liquid material coated in a display area. There is provided an organic EL device in which a plurality of pixels XR, XG, XB is arranged in an effective display area of a substrate and each of the pixels XR, XG, XB is provided with a first organic EL element having a functional film formed by a liquid phase method, wherein a dummy area D having a plurality of dummy pixels D 1 R, D 1 G, D 1 B, D 2 R, D 2 G, D 2 B for inspection of characteristics is provided around the effective display area and each dummy pixel is provided with a second organic EL element having a functional film formed using the same process as the functional film of the first organic EL element. US2019/348478A1 describes a display device, an apparatus for testing a display device, and a method for testing a display device. A display device includes a first substrate having a display area and a non-display area defined thereon, the non-display area being on an outer side of the display area. The non-display area may include a plurality of test pads and a first dummy thin-film transistor electrically connected to the test pads. The first dummy thin-film transistor includes a dummy gate electrode, and a dummy source electrode and a dummy drain electrode insulated from the gate electrode and spaced apart from each other. A bending area is defined on the first substrate that at least partially traverses the display area and the non-display area, the bending area overlaps the first dummy thin-film transistor. CN110473895A describes an OLED display substrate and a manufacturing method thereof, and a display device, relates to the technical field of OLED display, and aims to reduce the risk that metal wires used for wire binding between an OLED display panel and an external circuit fall off. The OLED display substrate comprises a binding area and a display area. The binding area comprises a plurality of first signal via holes for providing binding lead channels, the display area comprises a plurality of second signal via holes for providing electrode lead channels, and the aperture of each of the plurality of first signal via holes is larger than that of each of the plurality of second signal via holes. The manufacturing method of the OLED display substrate is used for manufacturing the OLED display substrate. The OLED display substrate and the manufacturing method of the OLED display substrate and the display device are used in the display technology. WO2017/063568A1 describes an array substrate, its manufacturing method, and a display apparatus. The array substrate includes a monocrystalline silicon layer (11) and an array circuit layer (12). The array circuit layer is disposed over the monocrystalline silicon layer. The array circuit layer comprises a scan drive circuit (12b), a data drive circuit (12c), and a plurality of pixel circuits (12a). The scan drive circuit and the data drive circuit are configured to respectively control a plurality of scan lines and a plurality of data lines to in turn drive a plurality of pixels. Each of the plurality of pixel circuits is configured to drive one of the plurality of pixels to emit light under control of at least one of the plurality of scan lines and at least one of the plurality of data lines; and the scan drive circuit, the data drive circuit, and the plurality of pixel circuits comprise a plurality of thin film transistors (TFTs), each having an active region disposed in the monocrystalline silicon layer. SUMMARY The present invention comprises a display panel in accordance with claim 1 and a display device in accordance with claim 15. According to an aspect of the present disclosure, a display panel is provided, including: A driving backplane, having a pixel driving region and a peripheral region surrounding the pixel driving region, and the