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EP-4131413-B1 - DISPLAY PANEL AND DISPLAY APPARATUS

EP4131413B1EP 4131413 B1EP4131413 B1EP 4131413B1EP-4131413-B1

Inventors

  • SHANG, TINGHUA
  • LIU, Biao
  • LIU, Tingliang
  • YANG, HUIJUAN
  • LIAO, Maoying
  • ZHANG, YI

Dates

Publication Date
20260506
Application Date
20210330

Claims (12)

  1. A display panel comprising a pixel driving circuit, in which the display panel further comprises: a base substrate; a second conductive layer, disposed on a side of the base substrate and comprising multiple first signal lines (V1), wherein orthographic projections of the multiple first signal lines (V1) on the base substrate extend in a first direction (X) and are spaced apart in a second direction (Y), and an orthographic projection of the first direction (X) on the base substrate and an orthographic projection of the second direction (Y) on the base substrate intersect; and a third conductive layer, disposed on a side of the second conductive layer away from the base substrate and comprising multiple second signal lines (V2), wherein orthographic projections of the multiple second signal lines (V2) on the base substrate extend in the second direction (Y) and are spaced apart in the first direction (X); wherein the first signal lines (V1) and the second signal lines (V2) are configured to provide a same first signal to the pixel driving circuit, and at least part of the first signal lines (V1) and at least part of the second signal lines (V2) are coupled through via holes; wherein the second conductive layer further comprises multiple third signal lines (V3), wherein orthographic projections of the multiple third signal lines (V3) on the base substrate extend in the first direction (X) and are spaced apart in the second direction (Y); and the third conductive layer further comprises multiple fourth signal lines (V4), wherein orthographic projections of the multiple fourth signal lines (V4) on the base substrate extend in the second direction (Y) and are spaced apart in the first direction (X); wherein the third signal lines and the fourth signal lines (V4) are configured to provide a same second signal to the pixel driving circuit, and at least part of the third signal lines (V3) and at least part of the fourth signal lines (V4) are coupled through via holes; wherein the display panel comprises a light emitting unit (OLED) driven by the pixel driving circuit, and the pixel driving circuit comprises multiple transistors, the display panel further comprises: an active layer, disposed between the base substrate and the second conductive layer, at least part of a structure of the active layer is configured to form channel regions of at least part of the transistors, and the active layer comprises: multiple first active part groups (4) spaced apart in the first direction (X), wherein the first active part group (4) comprises: multiple first active parts (41), wherein orthographic projections of the multiple first active parts (41) on the base substrate are spaced apart in the second direction (Y), and the orthographic projection of the first active part (41) on the base substrate extends in the second direction (Y); wherein the multiple second signal lines (V2) are arranged in a one-to-one correspondence with a part of the first active part groups (4), and the second signal line (V2) comprises: multiple first extension parts (V21), arranged in a one-to-one correspondence with the first active parts (41), wherein orthographic projections of the first extension parts (V21) on the base substrate extend in the second direction (Y), and any segment of the orthographic projection of the first extension parts (V21) on the base substrate in the extension direction of the first extension part (V21) is at least partially overlapped with an orthographic projection of the first active part (41) corresponding to the first extension part (V21) on the base substrate; and a second extension part (V22), coupled between two adjacent first extension parts (V21), wherein an orthographic projection of the second extension part (V22) on the base substrate is not overlapped with the orthographic projections of the first active parts (41) on the base substrate.
  2. The display panel according to claim 1, wherein the multiple transistors comprise: a driving transistor (T3), configured to output a driving current to a first electrode of the driving transistor (T3) based on a voltage of a gate of the driving transistor (T3); a second transistor (T2), comprising: a second electrode coupled to the gate of the driving transistor (T3), a first electrode coupled to the first electrode of the driving transistor (T3), and a gate coupled to a gate driving signal terminal; a sixth transistor (T6), comprising: a first electrode coupled to the first electrode of the driving transistor (T3), a second electrode coupled to a first electrode of the light emitting unit (OLED), and a gate coupled to an enable signal terminal (EM); and a seventh transistor (T7), comprising: a first electrode, configured to receive a second initial signal; and a second electrode coupled to the first electrode of the light emitting unit (OLED); wherein a part of a structure of the first active part (41) is configured to form a first channel region of the second transistor (T2), and channel regions of the sixth transistor (T6) and the seventh transistor (T7).
  3. The display panel according to claim 1, wherein the display panel comprises a light emitting unit (OLED) driven by the pixel driving circuit, and the pixel driving circuit comprises a seventh transistor (T7), a first electrode of the seventh transistor (T7) is configured to receive a second initial signal, a second electrode is configured to be coupled to a first electrode of the light emitting unit (OLED); and the first signal lines (V1) and the second signal lines (V2) are configured to provide the second initial signal to the first electrode of the seventh transistor (T7).
  4. The display panel according to claim 1, wherein the multiple fourth signal lines (V4) are arranged in a one-to-one correspondence with a part of the first active part groups (4), and the fourth signal line (V4) comprises: multiple third extension parts (V43), arranged in a one-to-one correspondence with the first active parts (41), wherein an orthographic projection of the third extension part (V43) on the base substrate extends in the second direction (Y), and any segment of the orthographic projection of the third extension part (V43) on the base substrate in the extension direction thereof is at least partially overlapped with an orthographic projection of the first active part (41) corresponding to the third extension part (V43) on the base substrate; wherein the fourth signal line (V4) further comprises: a fourth extension part (V44), coupled between adjacent third extension parts (V43), wherein an orthographic projection of the fourth extension part (V44) on the base substrate extends in the first direction (X), and any segment of the orthographic projection of the fourth extension part (V44) on the base substrate in the extension direction thereof is at least partially overlapped with the orthographic projection of the third signal line (V3) on the base substrate.
  5. The display panel according to claim 4, wherein the multiple transistors comprises a driving transistor (T3) and a first transistor (T1), a second electrode of the first transistor (T1) is configured to receive a first initial signal, and a first electrode of the first transistor (T1) is coupled to a gate of the driving transistor (T3), and the active layer further comprises: a second active part (42), wherein an orthographic projection of the second active part (42) on the base substrate extends in the second direction (Y), and the second active part (42) comprises a first sub-active part (421) configured to form a first channel region of the first transistor (T1); and the fourth signal line (V4) further comprises: a fifth extension part (V45), coupled between the fourth extension part (V44) and the third extension part (V43) that are adjacent to each other, wherein an orthographic projection of the fifth extension part (V45) on the base substrate extends in the second direction (Y), and any segment of the orthographic projection of the fifth extension part (V45) on the base substrate in the extension direction thereof is at least partially overlapped with an orthographic projection of the second active part (42) on the base substrate.
  6. The display panel according to claim 1, wherein the pixel driving circuit comprises a driving transistor (T3) and a first transistor (T1), a second electrode of the first transistor (T1) is configured to receive a first initial signal, and a first electrode of the first transistor (T1) is coupled to a gate of the driving transistor (T3); and the third signal lines (V3) and the fourth signal lines (V4) are configured to provide the first initial signal.
  7. The display panel according to claim 5, wherein the active layer further comprises: a second sub-active part (422), configured to form a second channel region of the first transistor (T1); and a third sub-active part (423), coupled between the first sub-active part (421) and the second sub-active part (422), wherein an orthographic projection of the third sub-active part (423) on the base substrate extends in the first direction (X); wherein the orthographic projection of the first signal line (V1) on the base substrate is at least partially overlapped with the orthographic projection of the third sub-active part (423) on the base substrate.
  8. The display panel according to claim 7, wherein the multiple transistors further comprises: a second transistor (T2), comprising: a second electrode coupled to the gate of the driving transistor (T3), a first electrode coupled to the first electrode of the driving transistor (T3), and a gate coupled to a gate driving signal terminal; the first active part (41) further comprises: a fourth sub-active part (414), configured to form a first channel region of the second transistor (T2); the active layer further comprises: a fifth sub-active part (415), configured to form a second channel region of the second transistor (T2); and a sixth sub-active part (416), coupled between the fourth sub-active part (414) and the fifth sub-active part (415); the second conductive layer further comprises: multiple first conductive parts (21), wherein the first conductive part (21) comprises a first sub-conductive part (211), an orthographic projection of the first sub-conductive part (211) on the base substrate is at least partially overlapped with an orthographic projection of the sixth sub-active part (416) on the base substrate.
  9. The display panel according to claim 8, wherein the fourth signal line (V4) further comprises: a sixth extension part (V46), coupled between the fifth extension part (V45) and the third extension part (V43) that are adjacent to each other; the first conductive part (21) further comprises: a second sub-conductive part (212), coupled to the first sub-conductive part (211), wherein in the second direction (Y), an orthographic projection of the second sub-conductive part (212) on the base substrate is disposed between orthographic projections of two adjacent first active parts (41) on the base substrate, and in the second direction (Y), the orthographic projection of the second sub-conductive part (212) on the base substrate is disposed between the orthographic projection of the second active part (42) on the base substrate and the orthographic projection of the first active part (41) on the base substrate; a part of the first conductive parts (21) are arranged correspondingly to the second signal lines (V2), and a part of the first conductive parts (21) are arranged correspondingly to the fourth signal lines (V4); an orthographic projection of the second sub-conductive part (212) arranged correspondingly to the second signal line (V2) on the base substrate is at least partially overlapped with an orthographic projection of the second extension part (V22) on the base substrate; and an orthographic projection of the second sub-conductive part (212) arranged correspondingly to the fourth signal line (V4) on the base substrate is at least partially overlapped with an orthographic projection of the sixth extension part (V46) on the base substrate; wherein the display panel further comprises: a first conductive layer disposed between the active layer and the second conductive layer, and the first conductive layer comprises: a second conductive part (12), configured to form the gate of the driving transistor (T3); and a gate driving signal line (Gate), wherein a part of the gate driving signal line (Gate) is configured to form a first gate of the second transistor (T2), an orthographic projection of the gate driving signal line (Gate) on the base substrate extends in the first direction (X), and the orthographic projection of the gate driving signal line (Gate) on the base substrate is disposed between an orthographic projection of the second conductive part (12) on the base substrate and the orthographic projection of the first signal line (V1) on the base substrate; the active layer further comprises: a seventh sub-active part (407), coupled between the fifth sub-active part (415) and the second sub-active part (422); the third conductive part further comprises: a first connection part (31), coupled to the seventh sub-active part (407) and the second conductive part (12) through via holes, respectively; the first conductive part (21) further comprises: a third sub-conductive part (213), coupled to the second sub-conductive part (212), wherein in the second direction (Y), an orthographic projection of the third sub-conductive part (213) on the base substrate is disposed between the orthographic projection of the second sub-conductive part (212) on the base substrate and an orthographic projection of the gate driving signal line (Gate) on the base substrate.
  10. The display panel according to claim 5, wherein the second signal lines (V2) and the fourth signal lines (V4) are alternately arranged in sequence in the first direction (X); the multiple second signal lines (V2) and the multiple fourth signal lines (V4) form multiple initial signal lines; and the second direction (Y) is a column direction, and each column of the pixel driving circuits is correspondingly coupled to one of the initial signal lines; wherein a pixel driving circuit correspondingly coupled to the second signal line (V2) is located in a red or blue sub-pixel unit, and a pixel driving circuit correspondingly coupled to the fourth signal line (V4) is located in a green sub-pixel unit.
  11. The display panel according to claim 1, wherein a sheet resistance of the second conductive layer is greater than a sheet resistance of the third conductive layer; wherein the third conductive layer further comprises: a power line (VDD), wherein an orthographic projection of the power line (VDD) on the base substrate extends in the second direction (Y), and the power line (VDD) is configured to provide a power signal.
  12. A display device, comprising the display panel according to any one of claims 1-11.

Description

TECHNICAL FIELD The present disclosure relates to the field of display technologies, and in particular, to a display panel and a display device. BACKGROUND In the related art, a display panel typically includes signal lines such as an initial signal line, an enable signal line, a data signal line, and a power line. However, since the signal lines have own resistances, signals transmitted on the signal lines have different voltage drops at different positions of the display panels, resulting in uneven display of the display panel. US7456811B2 relates to an organic electroluminescence device, which includes a power line formed on the same layer as source and drain electrodes of a thin film transistor (TFT) and formed on a substrate on which the TFT is formed, a first insulating layer formed on the TFT, a lower electrode that electrically connected to one of the source and drain electrodes of the TFT and disposed on the first insulating layer, a first auxiliary power line and a second auxiliary power line formed on the same layer as the lower electrode in the second insulating layer, a second insulating layer formed on an edge portion of the lower electrode and not formed on the second auxiliary power line, wherein an opening that exposes a portion of the lower electrode is formed, an organic film formed on a substrate; and an upper electrode formed on the substrate. It should be noted that the information disclosed in the Background section above is only for enhancing the understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY The present invention comprises a display panel and a display device as defined by the claims. Embodiments that do not fall within the scope of the claims should be interpreted as examples useful for understanding the invention. It should be noted that the above general description and the following detailed description are merely exemplary and explanatory and should not be construed as limiting of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS The drawings here are incorporated into the specification and constitute a part of the specification, show embodiments in accordance with the present disclosure, and are used together with the specification to explain the principle of the present disclosure. Apparantly, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work. FIG. 1 is a schematic diagram illustrating a circuit structure of a pixel driving circuit in a display panel according to an exemplary embodiment of the present disclosure;FIG. 2 is a timing diagram of each node in a driving method for the pixel driving circuit in FIG. 1;FIG. 3 is a structural layout diagram of a display panel according to an exemplary embodiment of the present disclosure;FIG. 4 is a structural layout diagram of a display panel according to another exemplary embodiment of the present disclosure;FIG. 5 is a structural layout diagram of a display panel according to an exemplary embodiment of the present disclosure;FIG. 6 is a structural layout of an active layer in FIG. 5;FIG. 7 is a structural layout of a first conductive layer in FIG. 5;FIG. 8 is a structural layout of a second conductive layer in FIG. 5;FIG. 9 is a structural layout of a third conductive layer in FIG. 5;FIG. 10 is a structural layout of a fourth conductive layer in FIG. 5;FIG. 11 is a structural layout of an anode layer in FIG. 5;FIG. 12 is a structural layout of an active layer and a first conductive layer in FIG. 5;FIG. 13 is a structural layout of an active layer, a first conductive layer, and a second conductive layer in FIG. 5;FIG. 14 is a structural layout of an active layer, a first conductive layer, a second conductive layer, and a third conductive layer in FIG. 5;FIG. 15 is a structural layout of an active layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer in FIG. 5;FIG. 16 is a partial cross-sectional view taken along a dotted line 'A' in FIG. 5; andFIG. 17 is a schematic structural diagram of a display panel according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be implemented in a variety of forms and should not be construed as being limited to the examples set forth herein; rather, these embodiments are provided so that the present disclosure will be more full and complete so as to convey the idea of the exemplary embodiments to those skilled in this art. The same reference numerals in the drawings denote the same or similar parts, and the repeated description thereof will be omitted. Although the relative terms such as