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EP-4132229-B1 - DISPLAY MODULE AND DISPLAY DEVICE

EP4132229B1EP 4132229 B1EP4132229 B1EP 4132229B1EP-4132229-B1

Inventors

  • BAI, Xiao
  • YANG, Shengji
  • HUANG, KUANTA
  • LU, Pengcheng

Dates

Publication Date
20260506
Application Date
20200327

Claims (14)

  1. A display, comprising: a circuit board structure (20), comprising a first circuit board (201) and a second circuit board (202); the first circuit board (201) having a carrying region (201a) and an electrical connection region (201b), and a first pad (2011) being disposed on the electrical connection region (201b); the second circuit board (202) having a first region (202a) and a second region (202b), the first region (202a) being arranged on the electrical connection region (201b) of the first circuit board (201) and being electrically connected to the first pad (2011), and the second region (202b) being configured to be electrically connected to a driving terminal; and a rigidity of the second circuit board (202) being less than a rigidity of the first circuit board (201); a display substrate (10), located on the carrying region (201a) of the first circuit board (201), the display substrate (10) comprising a silicon substrate (102), a driving circuit (100) and a second pad (101); at least part of the driving circuit (100) being embedded in the silicon substrate (102); the driving circuit (100) comprising a transistor having a semiconductor layer (1031), and the semiconductor layer (1031) being located inside the silicon substrate (102); the second pad (101) being electrically connected with the driving circuit (100), and the second pad (101) being electrically connected with the first pad (2011); wherein the first circuit board (201) comprises: a plurality of dielectric boards (2010), stacked in sequence; and at least one trace layer (2016), located in the electrical connection region (201b); the at least one trace layer (2016) is between adjacent ones of the plurality of dielectric boards (2010) and is electrically connected to the first pad (2011); the first region (202a) of the second circuit board (202) is located between adjacent dielectric boards (2010) and is electrically connected to the trace layer (2016).
  2. The display according to claim 1, wherein the first circuit board (201) further comprises a plurality of heat dissipation holes (2015), and the plurality of heat dissipation holes (2015) are in the carrying region (201a) and configured to penetrate through each dielectric board (2010).
  3. The display according to claim 2, wherein an aperture of each of the heat dissipation holes (2015) is 0.1 mm to 0.45 mm.
  4. The display according to claim 2, wherein: a heat dissipation layer (2018) is provided on opposite sides of each dielectric board (2010), and the heat dissipation layer (2018) is in the carrying region (201a); and each heat dissipation hole (2015) of the heat dissipation holes (2015) is configured to penetrate through each dielectric board (2010) while also penetrating each heat dissipation layer (2018).
  5. The display according to claim 4, wherein the heat dissipation hole (2015) is a hole structure filled with metal material; the heat dissipation layer (2018) is a metal heat dissipation layer (2018).
  6. The display according to claim 4, wherein an orthographic projection of the display substrate (10) on the dielectric board (2010) is configured to overlap an orthographic projection of the heat dissipation layer (2018) on the dielectric board (2010).
  7. The display according to any one of claims 1 to 6, wherein the plurality of dielectric boards (2010) stacked in sequence comprise a first dielectric board (2012), a second dielectric board (2013), and a third dielectric board (2014) that are sequentially stacked; wherein: the display substrate (10) and the first pad (2011) are on a side of the first dielectric board (2012) away from the second dielectric board (2013); the trace layer (2016) is between the first dielectric board (2012) and the second dielectric board (2013), and the trace layer (2016) is electrically connected to the first pad (2011) through a via hole (2017); the first region (202a) of the second circuit board (202) is between the second dielectric board (2013) and the third dielectric board (2014), and the first region (202a) is electrically connected to the trace layer (2016) through a via hole (2017).
  8. The display according to any one of claims 1 to 7, wherein the second circuit board (202) is a flexible circuit board.
  9. The display according to claim 8, wherein the second circuit board (202) comprises: a flexible base (2021); a wiring layer (2025), formed on the flexible base (2021), the wiring layer (2025) comprises a main wiring portion (2023) and a third pad (2024) electrically connected to the main wiring portion (2023), the third pad (2024) is in the first region (202a) and is electrically connected to the trace layer (2016), and the main wiring portion (2023) is in the second region (202b); and a protection portion (2022), located in the second region (202b) and formed on a side of the main wiring portion (2022) away from the flexible base (2021).
  10. The display according to claim 9, wherein: a material of the flexible base (2021) and the protection portion (2022) is polyimide, and a material of the wiring layer (2025) is a metal material; a material of the dielectric board (2010) is glass fiber, and a material of the trace layer (2016) is a metal material.
  11. The display according to claim 1, wherein the second pad (101) and the first pad (2011) are electrically connected through a metal lead (203); wherein the display further comprises a protective film layer (204), the protective film layer (204) covers the first pad (2011), the second pad (101) and the metal lead (203).
  12. The display according to claim 1, wherein: the display substrate (10) is configured to have a display region (10a) and a bonding region (10b) located at at least one side of the display region (10a), and the second pad (101) is in the bonding region (10b); the display substrate (10) further comprises a light-emitting element (104) located in the display region (10a), and the light-emitting element (104) is on a side of the driving circuit (100) away from a base substrate and electrically connected to the driving circuit (100).
  13. The display according to claim 1, wherein the driving circuit (100) further comprises a scanning signal line, a data signal line, and a power voltage signal line; wherein the power voltage signal line is electrically connected to the driving terminal through the second pad (101) and the circuit board structure (20).
  14. A display device, comprising the display according to any one of claims 1 to 13.

Description

TECHNICAL FIELD The present disclosure relates to the field of display technology, and in particular to a display and a display device. BACKGROUND In recent years, with the increasing progress of virtual reality (VR) technology and augmented reality (AR) technology, display devices suitable for the VR/AR field are also developing toward miniaturization, pixel per inch (PPI), fast response, and high color gamut. Silicon-based micro-display Organic Light-Emitting Diode (OLED) panel is one of the prominent directions. Although the silicon-based micro-display OLED started late, it is becoming a new focus of attention in the display field due to its advantages in miniaturization and high PPI. Because the Flexible Printed Circuit (FPC) is mainly used in the AR/VR field, in order to facilitate the assembly of modules, the flexible printed circuit (FPC) has become the main way to connect silicon-based OLEDs to the driving terminal. However, since the FPC often uses the anisotropic conductive film (ACF) bonding process to connect with silicon-based OLED, the reliability is poor. WO 2012/141117 A1 discloses a liquid crystal module provided with a liquid crystal panel and a backlight unit. The backlight unit is disposed on a wiring board and the wiring board has an elongated section extending further outward than the backlight unit. A first connection terminal is disposed on the elongated section. An array substrate has a bulging section bulging further than a color filter substrate, and a second connection terminal is disposed on the bulging section. The second connection terminal of the array substrate and the first connection terminal of the wiring board are coupled to one another by means of a wire bond. WO 2017/063568 A1 discloses an array substrate, its manufacturing method, and a display apparatus. The array substrate includes a monocrystalline silicon layer and an array circuit layer. The array circuit layer is disposed over the monocrystalline silicon layer. The array circuit layer comprises a scan drive circuit, a data drive circuit, and a plurality of pixel circuits. The scan drive circuit and the data drive circuit are configured to respectively control a plurality of scan lines and a plurality of data lines to in turn drive a plurality of pixels. Each of the plurality of pixel circuits is configured to drive one of the plurality of pixels to emit light under control of at least one of the plurality of scan lines and at least one of the plurality of data lines; and the scan drive circuit, the data drive circuit, and the plurality of pixel circuits comprise a plurality of thin film transistors, each having an active region disposed in the monocrystalline silicon layer. SUMMARY The present invention comprises a display and a display device as defined in the claims. Embodiments that do not fall within the scope of the claims are to be interpreted as examples useful for understanding the invention. The embodiments of the present disclosure provide a display and a display device with high reliability. In one embodiment of the present disclosure, a display is provided, the display including: A circuit board structure, including a first circuit board and a second circuit board; the first circuit board has a carrying region and an electrical connection region, and a first pad being disposed on the electrical connection region; the second circuit board has a first region and a second region, the first region is arranged on the electrical connection region of the first circuit board and is electrically connected to the first pad, and the second region is configured to be electrically connected to a driving terminal; and a rigidity of the second circuit board is less than a rigidity of the first circuit board; A display substrate, located on the carrying region of the first circuit board, the display substrate includes a silicon substrate, a driving circuit and a second pad; at least part of the driving circuit being embedded in the silicon substrate; the driving circuit includes a transistor having a semiconductor layer, and the semiconductor layer is located inside the silicon substrate; the second pad is electrically connected with the driving circuit, and the second pad is electrically connected with the first pad. In accordance with the claimed invention, the first circuit board includes: A plurality of dielectric boards, stacked in sequence; andAt least one trace layer, located in the electrical connection region; the at least one trace layer is located between adjacent ones of the plurality of dielectric boards and is electrically connected to the first pad;The first region of the second circuit board is located between adjacent dielectric boards and is electrically connected to the trace layer. In one exemplary embodiment of the present disclosure, the first circuit board further includes a plurality of heat dissipation holes, and the plurality of heat dissipation holes are located in the carrying region and