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EP-4135043-B1 - DISPLAY SUBSTRATE AND MANUFACTURING METHOD THEREFOR, AND DISPLAY DEVICE

EP4135043B1EP 4135043 B1EP4135043 B1EP 4135043B1EP-4135043-B1

Inventors

  • ZHOU, YANG
  • HUANG, Yao
  • ZHANG, Shun
  • YANG, HUIJUAN
  • HE, YUPENG
  • ZHANG, XIN
  • WANG, YU
  • SHANG, TINGHUA
  • ZHANG, YIYANG

Dates

Publication Date
20260506
Application Date
20210315

Claims (15)

  1. A display substrate (100), wherein the display substrate (100) has a display area (10a), the display area (10a) has a enclosed area (G1), the enclosed area (G1) includes a hole border area (10f), at least two wiring areas (10c), at least one through hole area (10d), and at least one blind hole area (10e), the at least one blind hole area (10e) is only in the display area (10a), and the at least one blind hole area (10e) is light-transmitting; a blind hole is provided in each blind hole area (10e), each through hole area (10d) and each blind hole area (10e) are both surrounded by a respective wiring area (10c) of the at least two wiring areas (10c), the hole border area (10f) surrounds the wiring areas (10c), and the display area (10a) surrounds the hole border area (10f), the display substrate (100) comprises: a base substrate (2), the base substrate (2) having a through hole (10) in each through hole area (10d); and a driving circuit layer (3) disposed on the base substrate (2), wherein the driving circuit layer (3) includes: at least one metal layer (31) located in the display area (10a), the hole border area (10f) and the wiring areas (10c), the at least one metal layer (31) including a plurality of signal lines, and the plurality of signal lines being disposed to avoid the at least one through hole area (10d) and the at least one blind hole area (10e); and at least one insulating layer (32) located in the display area (10a), the hole border area (10f), the wiring areas (10c) and the at least one blind hole area (10e); wherein the at least one through hole area (10d) includes two through hole areas (10d), the at least one blind hole area (10e) includes one blind hole area (10e), and the one blind hole area (10e) is disposed between the two through hole areas (10d).
  2. The display substrate (100) according to claim 1, wherein the through hole area (10d) is in a shape of a circle or a quasi-ellipse; and the blind hole area (10e) is in a shape of a rectangle, a rectangle with rounded corners, a shape formed by splicing rectangles with different widths together along a length direction thereof, or a shape formed by splicing rectangles with rounded corners with different widths together along a length direction thereof.
  3. The display substrate (100) according to claim 1 or 2, wherein the plurality of signal lines include a plurality of data lines (DL) and a plurality of gate drive signal lines (GL); the plurality of gate drive signal lines (GL) extend along a first direction (X) as a whole, and the plurality of data lines (DL) extend along a second direction (Y) as a whole, wherein the first direction (X) intersects the second direction (Y); at least one data line (DL) includes a portion located in a wiring area (10c) and making a detour around a through hole area (10d) surrounded by the wiring area (10c) and/or a portion located in a wiring area (10c) and making a detour around a blind hole area (10e) surrounded by the wiring area (10c); and at least one gate drive signal line (GL) includes a portion located in a wiring area (10c) and making a detour around a through hole area (10d) surrounded by the wiring area (10c) and/or a portion located in a wiring area (10c) and making a detour around a blind hole area (10e) surrounded by the wiring area (10c); and/or the plurality of signal lines further include a plurality of initialization signal lines (VINT); the plurality of initialization signal lines (VINT) extend along the first direction (X) as a whole; at least one initialization signal line (VINT) includes a portion located in a wiring area (10c) and making a detour around a through hole area (10d) surrounded by the wiring area (10c) and/or a portion located in a wiring area (10c) and making a detour around a blind hole area (10e) surrounded by the wiring area (10c); and/or the plurality of signal lines further include a plurality of light-emitting control signal lines (EL); the plurality of light-emitting control signal lines (EL) extend along the first direction (X) as a whole; at least one light-emitting control signal line (EL) includes a portion located in a wiring area (10c) and making a detour around a through hole area (10d) surrounded by the wiring area (10c) and/or a portion located in a wiring area (10c) and making a detour around a blind hole area (10e) surrounded by the wiring area (10c); or, at least one light-emitting control signal line (EL) includes a portion located in the display area (10a) and the hole border area (10f), and is cut off at a position, to which the light-emitting control signal line (EL) extends along the first direction (X), of a through hole area (10d) and/or a blind hold area (10e).
  4. The display substrate (100) according to any one of claims 1 to 3, wherein the at least one metal layer (31) includes a first gate layer (311), a second gate layer (312), and a source-drain metal layer (313); and the at least one insulating layer (32) includes a first insulating layer (321), a second insulating layer (322), and an interlayer insulating layer (323); the driving circuit layer (3) further includes a semiconductor layer (33), the semiconductor layer (33) is located in the display area (10a) and the hole border area (10f), wherein the semiconductor layer (33) is disposed on a side of the base substrate (2); the first insulating layer (321) is disposed on a side of the semiconductor layer (33) away from the base substrate (2); the first gate layer (311) is disposed on a side of the first insulating layer (321) away from the base substrate (2); the second insulating layer (322) is disposed on a side of the first gate layer (311) away from the base substrate (2); the second gate layer (312) is disposed on a side of the second insulating layer (322) away from the base substrate (2); the interlayer insulating layer (323) is disposed on a side of the second gate layer (312) away from the base substrate (2); and the source-drain metal layer (313) is disposed on a side of the interlayer insulating layer (323) away from the base substrate (2).
  5. The display substrate (100) according to claim 4, wherein in a case where the plurality of signal lines include a plurality of data lines (DL), a plurality of light-emitting control signal lines (EL), a plurality of gate drive signal lines (GL), and a plurality of initialization signal lines (VINT), the plurality of data lines (DL) are located in the source-drain metal layer (313); the plurality of light-emitting control signal lines (EL) and the plurality of gate drive signal lines (GL) are located in one of the first gate layer (311) and the second gate layer (312); and the plurality of initialization signal lines (VINT) are located in another of the first gate layer (311) and the second gate layer (312).
  6. The display substrate (100) according to claim 4 or 5, further comprising a light-emitting device layer (4) disposed on a side of the driving circuit layer (3) away from the base substrate (2), the light-emitting device layer (4) being located in the display area (10a) and the hole border area (10f), wherein the light-emitting device layer (4) includes: a first electrode layer (41) disposed on the side of the driving circuit layer (3) away from the base substrate (2), the first electrode layer (41) including a plurality of first electrodes (411); a pixel defining layer (44) disposed on a side of the first electrode layer (41) away from the base substrate (2), the pixel defining layer (44) being provided with a plurality of openings (K1) therein, and each opening (K1) exposing at least a portion of a first electrode (411); a functional layer (42) disposed on a side of the first electrode layer (41) away from the base substrate (2), the functional layer (42) including a plurality of light-emitting portions (421), and each light-emitting portion (421) being located in an opening (K1); and a second electrode layer (43) disposed on a side of the functional layer (42) and the pixel defining layer (44) away from the base substrate (2), wherein the display area (10a) is provided with a plurality of pixel structures (1) therein, and each pixel structure (1) includes a pixel circuit (11) and a light-emitting device (12); the light-emitting device (12) includes a first electrode (411) electrically connected to the pixel circuit (11), a light-emitting portion (421) in the plurality of light-emitting portions (421), and a portion of the second electrode layer (43) corresponding to the light-emitting portion (421); and the hole border area (10f) is provided with a plurality of redundant pixel structures (1') therein; each redundant pixel structure (1') includes a redundant pixel circuit (11') and/or a redundant light-emitting device (12'); the redundant light-emitting device (12') includes another light-emitting portion (421) in the plurality of light-emitting portions (421) and a portion of the second electrode layer (43) corresponding to the another light-emitting portion (421); or, the redundant light-emitting device (12') includes a first electrode (411), another light-emitting portion (421) in the plurality of light-emitting portions (421), and a portion of the second electrode layer (43) corresponding to the another light-emitting portion (421); and the first electrode (411) is not electrically connected to the redundant pixel circuit (11').
  7. The display substrate (100) according to claim 6, wherein each redundant pixel structure (1') includes the redundant pixel circuit (11'), the pixel circuit (11) and the redundant pixel circuit (11') both include at least one thin film transistor (T), each thin film transistor (T) includes an active layer (t1), a gate (t2), a source (t3), and a drain (t4); the active layer (t1) is located in the semiconductor layer (33), the gate (t2) is located in the first gate layer (311), and the source (t3) and the drain (t4) are located in the source-drain metal layer (313); the hole border area (10f) includes a first sub-area (10f1) proximate to a wiring area (10c), and a second sub-area (10f2) apart from the first sub-area (10f1); and the display substrate (100) further comprises: a plurality of via holes (K2) disposed in the second sub-area (10f2) of the hole border area (10f), each via hole (K2) penetrating the first insulating layer (321), the second insulating layer (322) and the interlayer insulating layer (323), the plurality of redundant pixel circuits (11') being disposed in the second sub-area (10f2) of the hole border area (10f), and the source (t3) and the drain (t4) of each thin film transistor (T) in the plurality of redundant pixel circuits (11') being electrically connected to the active layer (t1) thereof through via holes (K2); a plurality of redundant via holes (K3) disposed in the first sub-area (10f1) of the hole border area (10f), each redundant via hole (K3) penetrating the first insulating layer (321), the second insulating layer (322), and the interlayer insulating layer (323); and a planarization layer (5) disposed between the driving circuit layer (3) and the light-emitting device layer (4), the planarization layer (5) being located in the display area (10a), the hole border area (10f), the wiring areas (10c), and the at least one blind hole area (10e), and portions of the planarization layer (5) filling the plurality of redundant via holes (K3).
  8. The display substrate (100) according to claim 7, further having at least one encapsulation dam area (10g3), each encapsulation dam area (10g3) being located between a through hole area (10d) and a wiring area (10c) surrounding the through hole area (10d), and surrounding the through hole area (10d), wherein the first insulating layer (321), the second insulating layer (322), and the interlayer insulating layer (323) are further located in the at least one encapsulation dam area (10g3); and the display substrate (100) further comprises: one or more encapsulation dams (6), wherein each encapsulation dam area (10g3) is provided with at least one encapsulation dam (6) therein; the encapsulation dam (6) surrounds the through hole area (10d), and the encapsulation dam (6) is disposed on a side of the driving circuit layer (3) away from the base substrate (2); in a case where each encapsulation dam area (10g3) is provided with at least two encapsulation dams (6) therein, the at least two encapsulation dams (6) are disposed along a radial direction of the through hole area (10d) at intervals in sequence.
  9. The display substrate (100) according to claim 8, wherein the at least one encapsulation dam (6) provided in each encapsulation dam area (10g3) includes a first encapsulation dam (61) and a second encapsulation dam (62), and the first encapsulation dam (61) is located on a side of the second encapsulation dam (62) away from the through hole area (10d); a thickness of the second encapsulation dam (62) in a third direction (Z) is greater than a thickness of the first encapsulation dam (61) in the third direction (Z), the third direction (Z) is perpendicular to the base substrate (2); and the second encapsulation dam (62) includes: a first portion (62a), the first portion (62a) being disposed in a same layer as the planarization layer (5); a second portion (62b) disposed on a side of the first portion (62a) away from the base substrate (2), the second portion (62b) being disposed in a same layer as the pixel defining layer (44); and a first spacer (62c) disposed on a side of the second portion (62b) away from the base substrate (2); and the first encapsulation dam (61) includes: a third portion (61a), the third portion (61a) being disposed in a same layer as the pixel defining layer (44); and a second spacer (61b) disposed on a side of the third portion (61a) away from the base substrate (2), the second spacer (61b) being made of a same material and disposed in a same layer as the first spacer (62c).
  10. The display substrate (100) according to claim 9, further having at least one first isolation area (10g1) and at least one second isolation area (10g2), wherein the first insulating layer (321), the second insulating layer (322), and the interlayer insulating layer (323) are further located in the at least one first isolation area (10g1) and the at least one second isolation area (10g2); each first isolation area (10g1) is located between a wiring area (10c) and an encapsulation dam area (10g3), and surrounds the encapsulation dam area (10g3); and each second isolation area (10g2) is located between a through hole area (10d) and the encapsulation dam area (10g3), and surrounds the through hole area (10d); and the display substrate (100) further comprises: one or more first isolation pillars (7), each first isolation area (10g1) being provided with at least one first isolation pillar (7) therein, each first isolation pillar (7) being disposed to surround the first encapsulation dam (61) and being disposed on the side of the interlayer insulating layer (323) away from the base substrate (2), and a side wall of each first isolation pillar (7) being provided with a groove (70); and one or more second isolation pillars (8), each second isolation area (10g2) being provided with at least one second isolation pillar (8) therein, each second isolation pillar (8) being disposed to surround the through hole area (10d) and being disposed on the side of the interlayer insulating layer (323) away from the base substrate (2), and a side wall of each second isolation pillar (8) being provided with another groove (80).
  11. The display substrate (100) according to claim 10, wherein the at least one first isolation pillar (7) and the at least one second isolation pillar (8) are located in the source-drain metal layer (313); and/or each first isolation pillar (7) and each second isolation pillar (8) both include a first metal pattern (8a), a second metal pattern (8b), and a third metal pattern (8c) that are sequentially stacked; an outer boundary of an orthographic projection of the second metal pattern (8b) on the base substrate (2) is located with outer boundaries of orthographic projections of the first metal pattern (8a) and the third metal pattern (8c) on the base substrate (2), so as to form grooves (70 and 80) on side walls of each first isolation pillar (7) and each second isolation pillar (8); and/or each second isolation area (10g2) is further provided with at least one fourth metal pattern (8d) and at least one fifth metal pattern (8e) therein; the fourth metal pattern (8d) is located in the first gate layer (311), and the fifth metal pattern (8e) is located in the second gate layer (312); each fourth metal pattern (8d) and each fifth metal pattern (8e) surround the through hole area (10d); orthographic projections of a second isolation pillar (8), a fourth metal pattern (8d) corresponding to the second isolation pillar (8), and a fifth metal pattern (8e) corresponding to the second isolation pillar (8) on the base substrate (2) have a common overlapping area; and/or in a case where each first isolation area (10g1) is provided with at least two first isolation pillars (7) therein, the at least two first isolation pillars (7) are disposed along the radial direction of the through hole area (10d) at intervals in sequence; a portion, located between two adjacent first isolation pillars (7), of the driving circuit layer (3) has a slot (1d), and the slot (1d) exposes the base substrate (2); and in a case where each second isolation area (10g2) is provided with at least two second isolation pillars (8) therein, the at least two second isolation pillars (8) are disposed along the radial direction of the through hole area (10d) at intervals in sequence; and a portion, located between two adjacent second isolation pillars (8), of the driving circuit layer (3) has a recess (1f).
  12. The display substrate (100) according to claim 10 or 11, further comprising: an encapsulation layer (9) disposed on a side of the light-emitting device layer (4) away from the base substrate (2), wherein the encapsulation layer (9) includes: a first inorganic encapsulation film layer (91) disposed on the side of the light-emitting device layer (4) away from the base substrate (2), the first inorganic encapsulation film layer (91) being located in the at least one second isolation area (10g2), the at least one encapsulation dam area (10g3), the at least one first isolation area (10g1), the wiring areas (10c), the hole border area (10f), the display area (10a), and the at least one blind hole area (10e); an organic encapsulation film layer (92) disposed on a side of the first inorganic encapsulation film layer (91) away from the base substrate (2), the organic encapsulation film layer (92) being located in the at least one encapsulation dam area (10g3), the at least one first isolation area (10g1), the wiring areas (10c), the hole border area (10f), the display area (10a) and the at least one blind hole area (10e); and a second inorganic encapsulation film layer (93) disposed on a side of the organic encapsulation film layer (92) away from the base substrate (2), the second inorganic encapsulation film layer (93) being located in the at least one second isolation area (10g2), the at least one encapsulation dam area (10g3), the at least one first isolation area (10g1), the wiring areas (10c), the hole border area (10f), the display area (10a) and the at least one blind hole area (10e).
  13. A display apparatus (1000), wherein the display apparatus (1000) comprises: the display substrate (100) according to any one of claims 1 to 12; at least one first sensor (200), each first sensor (200) being disposed in a through hole area (10d); and at least one second sensor (300), each second sensor (300) being disposed in a blind hole area (10e).
  14. The display apparatus (1000) according to claim 13, wherein the at least one first sensor (200) includes a camera, and the at least one second sensor (300) includes at least one of an infrared sensor, a proximity optical sensor, a flood illuminator, and an ambient light sensor.
  15. A method for manufacturing a display substrate (100), the method comprising the steps of: providing a base substrate (2), the base substrate (2) including a display area (10a), the a display area (10a) having a enclosed area (G1), the enclosed area (G1) including a hole border area (10f), at least two wiring areas (10c), at least one through hole area (10d), and at least one blind hole area (10e), the at least one blind hole area (10e) being only in the display area (10a), the at least one blind hole area (10e) being light-transmitting, a blind hole being provided in each blind hole area (10e), each through hole area (10d) and each blind hole area (10e) being both surrounded by a respective wiring area (10c) of the at least two wiring areas (10c), the hole border area (10f) surrounding the wiring areas (10c), the display area (10a) surrounding the hole border area (10f), the at least one through hole area (10d) including two through hole areas (10d), the at least one blind hole area (10e) including one blind hole area (10e), and the one blind hole area (10e) being disposed between the two through hole areas (10d); forming a driving circuit layer (3) on the base substrate (2), the driving circuit layer (3) including: at least one metal layer (31) located in the display area (10a), the hole border area (10f) and the wiring areas (10c), the at least one metal layer (31) including a plurality of signal lines, and the plurality of signal lines being disposed to avoid the at least one through hole area (10d) and the at least one blind hole area (10e); and at least one insulating layer (32) located in the display area (10a), the hole border area (10f), the wiring areas (10c), the at least one through hole area (10d) and the at least one blind hole area (10e); forming a planarization layer (5) on a side of the driving circuit layer (3) away from the base substrate (2), the planarization layer (5) being located in the display area (10a), the hole border area (10f), the wiring areas (10c), the at least one through hole area (10d), and the at least one blind hole area (10e); forming a light-emitting device layer (4) on a side of the planarization layer (5) away from the base substrate (2), the light-emitting device layer (4) being at least located in the display area (10a) and the hole border area (10f); forming an encapsulation layer (9) on a side of the light-emitting device layer (4) away from the base substrate (2), the encapsulation layer (9) being located in the display area (10a), the hole border area (10f), the wiring areas (10c), the at least one through hole area (10d) and the at least one blind hole area (10e); and removing portions, located in the at least one through hole area (10d), of the base substrate (2), the driving circuit layer (3), the planarization layer (5), and the encapsulation layer (9).

Description

This application claims priority to International Patent Application No. PCT/CN2020/083829, filed on April 8, 2020. TECHNICAL FIELD The present disclosure relates to the field of display technologies, and in particular, to a display substrate and a method for manufacturing the same, and a display apparatus. BACKGROUND In display apparatuses, a groove or a via hole is generally formed in a flexible panel to meet users' requirements for an increasingly high screen-to-body ratio of electronic equipment products. At present, a relatively mature technology to achieve a high screen-to-body ratio of a display panel is the hole-in-display technology. The hole-in-display technology needs to sacrifice a part of a display area of the display panel, and the sacrificed display area is used for arranging optical sensors such as cameras. US 2020/106042 A1 provides a display device. The display device includes a first substrate including a display area and a non-display area, a display element disposed on the first substrate in the display area, a first sealing portion disposed on the first substrate in the non-display area, a second substrate facing the first substrate in a thickness direction, a hole defined through the first substrate and the second substrate along the thickness direction in the display area, and a second sealing portion disposed between the first substrate and the second substrate and enclosing the hole. SUMMARY In an aspect, the present disclosure provides a display substrate which is defined by claim 1. In another aspect, the present disclosure provides a display apparatus which is defined by claim 13. In yet another aspect, the present disclosure provides a method for manufacturing a display substrate which is defined by claim 15. BRIEF DESCRIPTION OF THE DRAWINGS In order to describe technical solutions in the present disclosure more clearly, accompanying drawings to be used in some embodiments of the present disclosure will be introduced briefly below. Obviously, the accompanying drawings to be described below are merely accompanying drawings of some embodiments of the present disclosure, and a person of ordinary skill in the art can obtain other drawings according to these drawings. In addition, the accompanying drawings to be described below may be regarded as schematic diagrams, but are not limitations on actual sizes of products, actual processes of methods and actual timings of signals involved in the embodiments of the present disclosure. FIG. 1 is a top view of a display substrate, in accordance with some embodiments of the present disclosure;FIG. 2 is a schematic diagram of an entire circuit architecture of a display substrate, in accordance with some embodiments of the present disclosure;FIG. 3 is an enlarged view of the area G1 in FIG. 1;FIG. 4 is another enlarged view of the area G1 in FIG. 1;FIG. 5 is yet another enlarged view of the area G1 in FIG. 1;FIG. 6 is a sectional view taken along the line A-A' in FIG. 3;FIG. 7 is a sectional view of a display substrate before a through hole area and a blind hole area are cut, in accordance with some embodiments of the present disclosure;FIG. 8A is a wiring diagram of an area G1 of a display substrate, in accordance with some embodiments of the present disclosure;FIG. 8B is another wiring diagram of an area G1 of a display substrate, in accordance with some embodiments of the present disclosure;FIG. 8C is yet another wiring diagram of an area G1 of a display substrate, in accordance with some embodiments of the present disclosure;FIG. 9 is an enlarged view of the area G2 in FIG. 4;FIG. 10 is an enlarged view of the area G7 in FIG. 9;FIG. 11 is an enlarged view of the area G3 in FIG. 4;FIG. 12 is an enlarged view of the area G8 in FIGS. 10 and 11 or the area G8' in FIG. 11;FIG. 13 is an equivalent circuit diagram of a pixel driving circuit in a display substrate, in accordance with some embodiments of the present disclosure;FIG. 14A is an enlarged view of the area G6 in FIG. 7;FIG. 14B is an enlarged view of the area G4' in FIG. 7;FIG. 15 is a sectional view of a display area of a display substrate, in accordance with some embodiments of the present disclosure;FIG. 16 is a sectional view of a display area of another display substrate, in accordance with some embodiments of the present disclosure;FIG. 17 is a sectional view of a hole border area of a display substrate, in accordance with some embodiments of the present disclosure;FIG. 18 is a sectional view of a hole border area of another display substrate, in accordance with some embodiments of the present disclosure;FIG. 19 is an enlarged view of the area G4 in FIG. 7;FIG. 20 is an enlarged view of the area G5 in FIG. 7; andFIG. 21 is a flow diagram of a method for manufacturing a display substrate, in accordance with some embodiments of the present disclosure. DETAILED DESCRIPTION Technical solutions in some embodiments of the present disclosure will be described clearly and completely below