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EP-4141947-B1 - DISPLAY PANEL AND FABRICATION METHOD THEREFOR, AND DISPLAY DEVICE

EP4141947B1EP 4141947 B1EP4141947 B1EP 4141947B1EP-4141947-B1

Inventors

  • LIU, CHANGCHANG
  • SHI, LING
  • LIU, KE
  • CHEN, Yipeng
  • ZHANG, ZHENHUA
  • LU, HUI

Dates

Publication Date
20260506
Application Date
20210224

Claims (12)

  1. A display panel (10), comprising: a base substrate (101) provided with a first display region (101a) and a second display region (101b); a first auxiliary electrode layer (102), a first anode layer (103), a first light-emitting layer (104) and a first cathode layer (105) that are sequentially laminated, in a direction away from the base substrate (101), in the first display region (101a); and a second auxiliary electrode layer (106), a second anode layer (107), a second light-emitting layer (108), and a second cathode layer (109) that are sequentially laminated, in the direction away from the base substrate (101), in the second display region (101b); wherein the first auxiliary electrode layer (102) is connected to the first cathode layer (105) and the second auxiliary electrode layer (106), and the second cathode layer (109) is connected to the first cathode layer (105), the second cathode layer (109) is provided with at least one hollowed-out region; the display panel (10) further comprises a plurality of pixel circuits (110) disposed in the second display region (101b), and each of the pixel circuits (110) comprises at least one layer of opaque patterns (b); wherein the second auxiliary electrode layer (106) comprises a plurality of auxiliary electrode patterns (1061) electrically connected; and at least 50% of areas of orthographic projections of the at least one layer of opaque patterns (b) in at least one of the pixel circuits (110) onto the base substrate (101) is overlapped with orthographic projections of the auxiliary electrode patterns (1061) onto the base substrate (101); wherein the display panel (10) comprises a plurality of first connection electrodes (124) disposed in the second display region (101b), wherein the plurality of auxiliary electrode patterns (1061) are electrically connected by the plurality of first connection electrodes (124); the display panel (10) comprises an active layer (112), a buffer layer (111), a first gate insulation layer (114), a first gate layer (113), a second gate insulation layer (116), a second gate layer (115), an interlayer dielectric layer (117), a first source/drain layer (118), a passivation layer (119), and a first planarization layer (120) that are sequentially laminated, in the direction away from the base substrate (101), in both the first display region (101a) and the second display region (101b); the display panel (10) comprises a first conduction layer (125) disposed in a same layer as the first source/drain layer (118), and a second conduction layer (126) disposed in a same layer as the second gate layer (115), wherein the buffer layer (111), the first gate insulation layer (114), the second gate insulation layer (116) and the interlayer dielectric layer (117) are all provided with a first via hole, the second conduction layer (126) and the first conduction layer (125) being stacked in the first via hole and being electrically connected to the auxiliary electrode patterns (1061) through the first via holes; and the plurality of first connection electrodes (124) are disposed between the passivation layer (119) and the first planarization layer (120), the passivation layer (119) is provided with a second via hole corresponding to the first via hole, at least part of the first connection electrodes (124) is disposed in the second via hole and connected to the first conduction layer (125).
  2. The display panel (10) according to claim 1, wherein there is at least one of the orthographic projections of the auxiliary electrode patterns (1061) onto the base substrate (101) cover the orthographic projections of the at least one layer of opaque patterns (b) in at least one of the pixel circuits (110) onto the base substrate (101); or edges of the orthographic projection of the auxiliary electrode pattern (1061) onto the base substrate (101) are at least partially arc-shaped.
  3. The display panel (10) according to claim 1, wherein the auxiliary electrode pattern (1061) comprises a first pattern (10611) and a second pattern (10612); an orthographic projection of the first pattern (10611) onto the base substrate (101) is overlapped with 50% or more of the areas of the orthographic projections of the at least one layer of opaque patterns (b) in at least one of the pixel circuits (110) onto the base substrate (101); the second pattern (10612) is configured to be electrically connected to the auxiliary electrode patterns (1061) adjacent to the second pattern (10612); and the orthographic projection of the first pattern (10611) onto the base substrate (101) is circular.
  4. The display panel (10) according to claim 1, wherein the base substrate (101) is further provided with a peripheral region (101c) surrounding both the first display region (101a) and the second display region (101b); the first auxiliary electrode layer (102) and the first cathode layer (105) are further disposed in the peripheral region (101c), and a portion disposed in the peripheral region (101c) of the first auxiliary electrode layer (102) is electrically connected to a portion disposed in the peripheral region (101c) of the first cathode layer (105); an orthographic projection of the first auxiliary electrode layer (102) onto the base substrate (101) covers the first display region (101a); the peripheral region (101c) comprises a first region (101c1) and a second region (101c2) that are arranged oppositely and in parallel, as well as a third region (101c3) and a fourth region (101c4) that are arranged oppositely and in parallel, a direction in which the first region (101c1) extends is perpendicular to a direction in which the third region (101c3) extends, and a distance between the second display region (101b) and the first region (101c1) is less than a distance between the second display region (101b) and the second region (101c2); and wherein a portion disposed in the first region (101c1) of the first auxiliary electrode layer (102) is connected to a portion disposed in the first region (101c1) of the first cathode layer (105), a portion disposed in the third region (101c3) of the first auxiliary electrode layer (102) is connected to a portion disposed in the third region (101c3) of the first cathode layer (105), and a portion disposed in the fourth region (101c4) of the first auxiliary electrode layer (102) is connected to a portion disposed in the fourth region (101c4) of the first cathode layer (105); and a portion disposed in the second region (101c2) of the first auxiliary electrode layer (102) is not connected to a portion disposed in the second region (101c2) of the first cathode layer (105).
  5. The display panel (10) according to any one of claims 1 to 4, wherein the first source/drain layer (118) comprises a plurality of sets of first source/drain layer patterns corresponding to the pixel circuits (110), the active layer (112) comprises a plurality of sets of active patterns (1131) corresponding to the pixel circuits (110), the first gate layer (113) comprises a plurality of sets of first gate patterns (1151) corresponding to the pixel circuits (110), and the second gate layer (115) comprises a plurality of sets of second gate layer patterns corresponding to the pixel circuits (110); and the at least one layer of opaque patterns (b) of the pixel circuit (110) comprise one set of the first source/drain layer patterns disposed in the first source/drain layer (118), one set of the active patterns (1131) disposed in the active layer (112), one set of the first gate patterns (1151) disposed in the first gate layer (113), and one set of the second gate patterns disposed in the second gate layer (115).
  6. The display panel (10) according to claim 5, further comprisinga plurality of second connection electrodes (127) disposed between the passivation layer (119) and the first planarization layer (120), a first signal transmission layer (128) disposed in a same layer as the first source/drain layer (118), and a third conduction layer (129) disposed in a same layer as the first gate layer (113); the first gate insulation layer (114), the second gate insulation layer (116) and the interlayer dielectric layer (117) are all provided with a third via hole, and the first signal transmission layer (128) is electrically connected to the third conduction layer (129) through the third via hole; and the passivation layer (119) is provided with a fourth via hole, and at least part of the second connection electrodes (127) is disposed in the fourth via hole and connected to the first signal transmission layer (128).
  7. The display panel (10) according to claim 6, wherein the third conduction layer (129) comprises a plurality of first signal line segments, a plurality of second signal line segments and a plurality of third signal line segments; wherein each signal line segment (1291) of the plurality of first signal line segments, the plurality of second signal line segments, and the plurality of third signal line segments is connected to one of the pixel circuits (110); the plurality of second connection electrodes (127) comprise a plurality of first-type second connection electrodes connected to the plurality of first signal line segments, a plurality of second-type second connection electrodes connected to the plurality of second signal line segments, and a plurality of third-type second connection electrodes connected to the plurality of third signal line segments; and the plurality of first signal line segments are gate signal line segments for transmitting gate signals, the plurality of second signal line segments are reset control signal line segments for transmitting reset control signals, and the plurality of third signal line segments are emission control signal line segments for transmitting emission control signals.
  8. The display panel (10) according to claim 5, further comprising a plurality of third connection electrodes (130), and a fourth conduction layer (131), wherein the fourth conduction layer (131) comprises a plurality of fourth signal line segments (1311); and each of the fourth signal line segments (1311) is connected to at least one of the pixel circuits (110), and at least part of the plurality of fourth signal line segments (1311) are electrically connected by at least part of the third connection electrodes (130).
  9. The display panel (10) according to claim 8, further comprising a second source/drain layer (121) disposed on a side, distal from the first source/drain layer (118), of the first planarization layer (120), wherein the fourth conduction layer (131) and the first source/drain layer (118) are disposed in a same layer, and the plurality of third connection electrodes (130) are disposed between the passivation layer (119) and the first planarization layer (120); further comprising a fifth conduction layer (132) disposed in a same layer as the second source/drain layer (121); wherein the fifth conduction layer (132) comprises a plurality of fifth signal line segments (1321), and the passivation layer (119) is provided with a fifth via hole; wherein at least part of the third connection electrodes (130) is disposed in the fifth via hole and connected to the fourth signal line segments (1311), the first planarization layer (120) is provided with a sixth via hole, and at least part of the fifth signal line segments (1321) is disposed in the sixth via hole and connected to the third connection electrodes (130); and the plurality of fourth signal line segments (1311) and the plurality of fifth signal line segments (1321) are all positive power signal line segments for transmitting positive power signals.
  10. The display panel (10) according to any one of claims 1 to 4, wherein the second anode layer (107) comprises a plurality of anode patterns spaced apart from each other, and the display panel (10) further comprises a pixel definition layer (134) disposed on a side, distal from the base substrate (101), of the second anode layer (107); the pixel definition layer (134) is provided with a plurality of tenth via holes, through which the corresponding anode patterns are exposed, and the second light-emitting layer (108) comprises a plurality of light-emitting layer patterns (1081) at least partially disposed in the tenth via holes; and the second cathode layer (109) at least partially covers the tenth via holes, and the at least one hollowed-out region of the second cathode layer (109) is not overlapped with the tenth via holes.
  11. The display panel (10) according to any one of claims 1 to 4, wherein a boundary of the at least one hollowed-out region at least partially comprises an arc shape; the first cathode layer (105) and the second cathode layer (109) are of an integral structure; and an area of an overlap between an orthographic projection of the hollowed-out region onto the base substrate (101) and the orthographic projections of the auxiliary electrode patterns (1061) onto the base substrate (101) is 10% smaller than an area of the hollowed-out region.
  12. A display device, characterized in that the display device comprises an image sensor (40) and the display panel (10) as defined in any one of claims 1 to 11, wherein the image sensor (40) is disposed on a side, distal from the second auxiliary electrode layer (106), of the base substrate (101) in the display panel (10), and is overlapped with the second display region (101b) of the base substrate (101).

Description

TECHNICAL FIELD The present disclosure relates to the field of display technologies and in particular relates to a display panel and a display device. BACKGROUND Organic light-emitting diode (OLED) display panels have been widely used due to their advantages of self-luminescence, low driving voltage, fast response, etc. US2020258947A1 describes a display apparatus. US2016322595A1 describes an organic light emitting display device. CN112259588A describes a displaying base plate. SUMMARY The present disclosure provides a display panel, and a display device. The technical solutions are described below and defined in the appended claims. In one aspect, a display panel is provided. The display panel includes: a base substrate provided with both a first display region and a second display region; a first auxiliary electrode layer, a first anode layer, a first light-emitting layer, and a first cathode layer that are sequentially laminated, in a direction away from the base substrate, in the first display region; and a second auxiliary electrode layer, a second anode layer, a second light-emitting layer and a second cathode layer that are sequentially laminated, in the direction away from the base substrate, in the second display region; wherein the first auxiliary electrode layer is connected to the first cathode layer and the second auxiliary electrode layer, and the second cathode layer is connected to the first cathode layer, the second cathode layer is provided with at least one hollowed-out region; the display panel further includes a plurality of pixel circuits disposed in the second display region, and each of the pixel circuits includes at least one layer of opaque patterns; wherein the second auxiliary electrode layer includes a plurality of auxiliary electrode patterns electrically connected; and at least 50% of regions of orthographic projections of the at least one layer of opaque patterns in at least one of the pixel circuits onto the base substrate is overlapped with orthographic projections of the auxiliary electrode patterns onto the base substrate, and the display panel includes a plurality of first connection electrodes disposed in the second display region, wherein the plurality of auxiliary electrode patterns are electrically connected by the plurality of first connection electrodes; the display panel includes an active layer, a buffer layer, a first gate insulation layer, a first gate layer, a second gate insulation layer, a second gate layer, an interlayer dielectric layer, a first source/drain layer, a passivation layer, and a first planarization layer that are sequentially laminated, in the direction away from the base substrate, in both the first display region and the second display region; the display panel includes a first conduction layer disposed in a same layer as the first source/drain layer, and a second conduction layer disposed in a same layer as the second gate layer, wherein the buffer layer, the first gate insulation layer, the second gate insulation layer and the interlayer dielectric layer are all provided with a first via hole, the second conduction layer and the first conduction layer being stacked in the first via hole and being electrically connected to the auxiliary electrode patterns through the first via holes; and the plurality of first connection electrodes are disposed between the passivation layer and the first planarization layer, the passivation layer is provided with a second via hole corresponding to the first via hole, at least part of the first connection electrodes is disposed in the second via hole and connected to the first conduction layer. In another aspect, a display device is provided. The display device includes an image sensor and the display panel as described in the foregoing aspect, wherein the image sensor is disposed on a side, distal from a second anode layer, of a base substrate in the display panel and is overlapped with a second display region of the base substrate. BRIEF DESCRIPTION OF THE DRAWINGS For clearer descriptions of the technical solutions in the embodiments of the present disclosure, the following briefly introduces the accompanying drawings required for describing the embodiments. Apparently, the accompanying drawings in the following description show merely some embodiments of the present disclosure, and a person of ordinary skill in the art may still derive other drawings from these accompanying drawings without creative efforts and while remaining within the scope of protection defined by the appended claims. FIG. 1 is a schematic structural diagram of a display panel according to some embodiments of the present disclosureFIG. 2 is a top view of a base substrate according some embodiments of the present disclosure;FIG. 3 is a schematic structural diagram of another display panel according to some embodiments of the present disclosure;FIG. 4 is a top view of a display panel according to some embodiments of the present disclos