EP-4150573-B1 - DESIGN-TO-WAFER IMAGE CORRELATION BY COMBINING INFORMATION FROM MULTIPLE COLLECTION CHANNELS

Inventors

• VARKEY, SUNIL
• GAWHANE, Dhiraj Ramesh

Dates

Publication Date

20260513

Application Date

20210609

Claims (11)

1. A method comprising: generating at least three dark field images of a feature on a semiconductor wafer using an optical inspection system (200), wherein each of the at least three dark field images are from different channels of the optical inspection system, and characterised in that , an aperture for each of the channels in the optical inspection system is fully open, meaning that the aperture is configured to allow the maximum possible light and information capture from the wafer without blocking any part of the light path during the generating; fusing the at least three dark field images to form a pseudo wafer image using a processor (214); and aligning the pseudo wafer image with a corresponding design using the processor (214); wherein the different channels include at least one side channel (212) and at least one top channel (209).
2. The method of claim 1, further comprising importing care areas for inspection to the pseudo wafer image using the processor (214).
3. The method of claim 2, further comprising determining placement accuracy of the care areas using the processor.
4. An optical inspection system (200) comprising: a stage (206) configured to hold a semiconductor wafer; a light source (203) that generates light directed to the stage (206); optics (204, 205) that receive light from the semiconductor wafer on the stage (206) and provide three channels (209, 212, 218); three apertures that receive light from the semiconductor wafer on the stage, wherein each of the three apertures receives the light from a different one of the three channels; three detectors that receive light from the semiconductor wafer on the stage, wherein each of the three detectors receives the light from a different one of the three channels (209, 212, 218);; and a processor (214) in electronic communication with the three detectors, wherein the processor is configured to: generate at least three dark field images of a feature on the semiconductor wafer, wherein each of the three dark field images is from a different one of the three channels; characterised by being configured to, fuse the at least three dark field images to form a pseudo wafer image; and align the pseudo wafer image with a corresponding design, wherein the apertures are fully open during the generating, and wherein the three channels include at least one side channel and at least one top channel.
5. The optical inspection system of claim 4, wherein the light source (203) includes a laser.
6. The optical inspection system of claim 4, wherein the processor is further configured to import care areas for inspection to the pseudo wafer image.
7. The optical inspection system of claim 6, wherein the processor is further configured to determine placement accuracy of the care areas.
8. A non-transitory computer-readable storage medium, comprising one or more programs for executing the following steps on one or more computing devices: characterised by , fusing at least three dark field images to form a pseudo wafer image, wherein the at least three dark field images include a feature on a semiconductor wafer formed using an optical inspection system (200), wherein each of the at least three dark field images are from different channels of the optical inspection system, and wherein an aperture for each of the channels in the optical inspection system is fully open for the at least three dark field images; and aligning the pseudo wafer image with a corresponding design; wherein the different channels include at least one side channel and at least one top channel.
9. The non-transitory computer-readable storage medium of claim 8, wherein the steps further include determining placement accuracy using care areas.
10. The non-transitory computer-readable storage medium of claim 8, wherein the steps further include importing care areas for inspection to the pseudo wafer image.
11. The non-transitory computer-readable storage medium of claim 10, wherein the steps further include determining placement accuracy of the care areas.

Description

FIELD OF THE DISCLOSURE This disclosure relates to semiconductor inspection. BACKGROUND OF THE DISCLOSURE Evolution of the semiconductor manufacturing industry is placing greater demands on yield management and, in particular, on metrology and inspection systems. Critical dimensions continue to shrink, yet the industry needs to decrease time for achieving high-yield, high-value production. Minimizing the total time from detecting a yield problem to fixing it maximizes the return-on-investment for a semiconductor manufacturer. Fabricating semiconductor devices, such as logic and memory devices, typically includes processing a semiconductor wafer using a large number of fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a photoresist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing (CMP), etching, deposition, and ion implantation. An arrangement of multiple semiconductor devices fabricated on a single semiconductor wafer may be separated into individual semiconductor devices. Inspection processes are used at various steps during semiconductor manufacturing to detect defects on wafers to promote higher yield in the manufacturing process and, thus, higher profits. Inspection has always been an important part of fabricating semiconductor devices such as integrated circuits (ICs). However, as the dimensions of semiconductor devices decrease, inspection becomes even more important to the successful manufacture of acceptable semiconductor devices because smaller defects can cause the devices to fail. For instance, as the dimensions of semiconductor devices decrease, detection of defects of decreasing size has become necessary because even relatively small defects may cause unwanted aberrations in the semiconductor devices. As design rules shrink, however, semiconductor manufacturing processes may be operating closer to the limitation on the performance capability of the processes. In addition, smaller defects can have an impact on the electrical parameters of the device as the design rules shrink, which drives more sensitive inspections. As design rules shrink, the population of potentially yield-relevant defects detected by inspection grows dramatically, and the population of nuisance defects detected by inspection also increases dramatically. Therefore, more defects may be detected on the wafers, and correcting the processes to eliminate all of the defects may be difficult and expensive. Determining which of the defects actually have an effect on the electrical parameters of the devices and the yield may allow process control methods to be focused on those defects while largely ignoring others. Furthermore, at smaller design rules, process-induced failures, in some cases, tend to be systematic. That is, process-induced failures tend to fail at predetermined design patterns often repeated many times within the design. Elimination of spatially-systematic, electrically-relevant defects can have an impact on yield. Wafer images may need to be aligned to a design file of the wafer for inspection and defect detection. Design alignment was performed using a wafer image from one collection channel. Only certain information can be collected using one channel. If design information is supposed to be aligned with a wafer image under these conditions, there is a possibility of inaccuracy during alignment of the wafer image and design file. This will result in incorrect placement of care areas in later inspection steps. Therefore, new techniques for wafer inspection are needed. In US 2019/361363 A1 alignment can be monitored by positioning at least one alignment verification location per alignment frame. The alignment verification location is a coordinate within the alignment frame. A distance between each of the alignment verification locations and a closest instance of an alignment target is determined. An alignment score can be determined based on the distance. The alignment score can include a number of the alignment frames between the alignment verification location and the alignment target. If the alignment score is below a threshold, then alignment setup can be performed. US 2012/268735 A1 relates to systems and methods for detecting defects on a wafer. One method includes generating output for a wafer by scanning the wafer with an inspection system using first and second optical states of the inspection system. The first and second optical states are defined by different values for at least one optical parameter of the inspection system. The method also includes generating first image data for the wafer using the output generated using the first optical state and second image data for the wafer using the output generated using the second optical stat