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EP-4167275-B1 - A METHOD FOR FORMING AN INTERCONNECTION STRUCTURE AND CORRESPONDING INTERCONNECT STRUCTURE

EP4167275B1EP 4167275 B1EP4167275 B1EP 4167275B1EP-4167275-B1

Inventors

  • HIBLOT, GASPARD

Dates

Publication Date
20260513
Application Date
20211018

Claims (12)

  1. A method for forming an interconnection structure for a first transistor and a second transistor vertically stacked on a substrate (100), wherein the first transistor includes a horizontally extending first channel portion (112) and the second transistor includes a horizontally extending second (122) channel portion, and wherein the first channel portion is arranged above the second channel portion, the method comprising: forming, in the substrate, a conductive line (130) extending beside and below the second channel portion; forming, on the conductive line, a first vertical interconnect structure (132) being electrically contacted to the first channel portion; thinning the substrate from the backside to expose the conductive line from below; forming a via hole (146) exposing the second channel portion from below; filling the via hole with a conductive material to form a second vertical interconnect structure (142); and forming a conductive structure (140) on the second vertical interconnect structure.
  2. The method according to claim 1, further comprising: depositing an insulating layer (150) covering the conductive line and the first and second channel portions; etching a trench (152) in the insulating layer to expose the conductive line and the first and second channel portions; forming spacers (154) at sidewalls of the first and second channel portions; and filling the trench with a conductive material forming the first vertical interconnect structure contacting the first channel portion at least partly from above.
  3. The method according to claim 1 or 2, further comprising: forming a bonding layer (160) above the first vertical interconnect structure; bonding a carrier wafer (162) to the bonding layer; and flipping the substrate upside down to allow processing from the backside of the substrate.
  4. The method according to claim 3, further comprising: forming, from the backside, a trench (144) that is aligned with the second channel portion; forming the via hole (146) in a bottom of the trench; and depositing the conductive material to fill the via hole and the trench, thereby forming the second vertical interconnect and the conductive structure.
  5. The method according to any of the preceding claims, wherein an exposed portion of the conductive line and an exposed portion of the conductive structure line are arranged on the same vertical level.
  6. The method according to any of the preceding claims, further comprising: epitaxially forming a stacked structure (102) comprising alternating layers of a channel material and a sacrificial material; patterning the stacked structure into a fin; and removing the layers of sacrificial material from at least a portion of the fin, wherein the remaining portions of the channel material form the first and second channel portions.
  7. The method according to claim 6, wherein the channel material is formed of Si and the sacrificial material is formed of SiGe.
  8. The method according to claim 6 or 7, further comprising forming a gate structure (134) at least partly enclosing the first and second channel portions.
  9. The method according to any of the preceding claims, wherein the substrate comprises an etch stop layer (104), and wherein forming the conductive lines comprises etching down to the etch stop layer.
  10. The method according to any of the preceding claims, comprising forming, in the substrate, a first and a second conductive line on opposite sides of the second channel portion, wherein the first vertical interconnect structure is arranged to interconnect the second channel portion with each of the first and second conductive lines.
  11. A semiconductor device, comprising: a first transistor and a second transistor vertically stacked on a substrate (100), wherein the first transistor includes a horizontally extending first channel portion (112) and the second transistor includes a horizontally extending second channel portion (122), and wherein the first channel portion is arranged above the second channel portion; a conductive line (130) arranged in the substrate and extending beside and below the second channel portion; a first vertical interconnect structure (132) arranged on the conductive line and being electrically contacted to the first channel portion; a conductive structure (140) arranged below the second channel portion, wherein a cross-section of the conductive line (130) and a cross-section of the conductive structure (140) are arranged in a same plane, the plane being orthogonal to a direction of the first and second channel portions; and a second vertical interconnect structure (142) extending between the second channel portion and the conductive structure.
  12. The semiconductor device according to claim 11, wherein a bottom portion of the conductive line and a bottom portion of the conductive structure are arranged at the same vertical level.

Description

Technical field The present inventive concept relates to semiconductor processing in general, and forming of an interconnection structure in particular. Background In the strive to provide even more area-efficient circuit designs, vertically stacked semiconductor devices are being developed. One example is the so-called complementary field-effect transistor, FET, design in which two horizontal channel transistors are stacked above each other, such that the horizontal channel portion of a first one of the transistors is arranged above the horizontal channel portion of a the other one of the transistors. The development of vertically stacked designs has however led to challenges in forming electrical interconnection structures for interconnecting devices and structures at different vertical levels. The interconnection structures, which may be arranged in an insulating material layer, may include horizontal conductive paths or lines on different interconnection levels, interconnected by conductive vias extending vertically between the levels. As the length of a conductive via varies with the vertical separation of the levels interconnected by the via, there is also a variation in electrical resistance between different vias. As the resistance tends to increase with increasing via length, it is challenging to balance the resistance between different vias and to avoid too high resistances between some interconnection levels. The publications WO2017/105515 A and US2021/242125 A disclose interconnect structures for stacked transistors according to the prior art. Summary It is an objective of the present inventive concept to provide an alternative method and device allowing for an interconnection structure preferably having improved electrical resistance properties. Further and alternative objectives may be understood from the following. According to an aspect of the present inventive concept, there is provided a method for forming an interconnection structure for a first transistor and a second transistor which are vertically stacked on a substrate, wherein the first transistor includes a horizontally extending first channel portion and the second transistor includes a horizontally extending second channel portion, and wherein the first channel portion is arranged above the second channel portion. The method comprises: forming, in the substrate, a conductive line extending beside and below the second channel portion;forming, on the conductive line, a first vertical interconnect structure being electrically contacted to the first channel portion;thinning the substrate from the backside to expose the conductive line from below;forming a via hole exposing the second channel portion from below;filling the via hole with a conductive material to form a second vertical interconnect structure; andforming a conductive structure on the second vertical interconnect structure. According to a second aspect there is provided a semiconductor device, comprising a first transistor and a second transistor vertically stacked on a substrate, wherein the first transistor includes a horizontally extending first channel portion and the second transistor includes a horizontally extending second channel portion, and wherein the first channel portion is arranged above the second channel portion. The semiconductor device further comprises a conductive line arranged in the substrate and extending beside and below the second channel portion, a first vertical interconnect structure arranged on the conductive line and and being electrically contacted to the first channel portion, a conductive structure arranged below the second channel portion, wherein a cross-section of the conductive line and a cross-section of the conductive structure are arranged in a same plane, the plane being orthogonal to a direction of the first and second channel portions,and a second vertical interconnect structure extending between the second channel portion and the conductive structure. The inventive technology allows for an alternative technology for forming the interconnection structure, wherein the first channel portion is interconnected to a first conductive line, which also may be referred to as a first buried power rail, by means of a first vertical interconnection structure formed on top of the buried power rail and extending all the way up to the vertical level of the first channel portion. The first vertical interconnection structure may be provided with lateral dimensions allowing for a specific electrical resistance to be obtained. Preferably, the lateral dimensions of the first vertical interconnection structure may be larger than those of a conventional via structure so as to reduce the electrical resistance. The inventive technology further allows for the second channel portion to be contacted from below by means of a second vertical interconnection structure. Thereafter, the second conductive line, which also may be referred to as a second buried int