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EP-4170644-B1 - PIXEL

EP4170644B1EP 4170644 B1EP4170644 B1EP 4170644B1EP-4170644-B1

Inventors

  • KWON, SOONGI
  • KWAK, WONKYU
  • KA, JIHYUN
  • KANG, CHULKYU
  • KIM, YANGWAN
  • EOM, KIMYEONG
  • OH, Kyonghwan
  • Lee, Minku
  • JEONG, JINTAE

Dates

Publication Date
20260513
Application Date
20221019

Claims (10)

  1. A display apparatus comprising a display unit (110) including pixels, wherein the display apparatus is configured to include a first initialization period, a data writing period, a second initialization period, and an emission period, wherein the second initialization period includes the first initialization period and/or the data writing period and wherein each pixel comprises: a display element (OLED) configured to emit light during the emission period and comprising an anode and a cathode; a first transistor (T1) comprising an upper gate (Ga) and a lower gate (Gb) and configured to control a magnitude of a driving current (Id) flowing to the display element (OLED); a storage capacitor (Cst) connected to the upper gate (Ga) of the first transistor (T1); a second transistor (T2) configured to be turned on during the data writing period to transmit a data voltage (Dm_j) to a source (S) of the first transistor (T1); a third transistor (T5) configured to be turned on during the emission period to transmit a driving voltage to a drain (D) of the first transistor (T1); a fourth transistor (T6) configured to be turned on during the emission period to connect the source (S) of the first transistor (T1) to the anode of the display element (OLED); and a fifth transistor (T7) configured to be turned on during the second initialization period to transmit an initialization voltage (VINT) to the anode of the display element (OLED); wherein the display apparatus is configured to turn on the second transistor (T2) and the fifth transistor (T7) during the data writing period and to turn on the fourth transistor (T6) during the emission period to apply a voltage difference (V GbS ) between the lower gate (Gb) and the source (S) of the first transistor (T1) having a first voltage level (V LEVEL 1) in the data writing period and a second voltage level (V LEVEL 2) in the emission period, wherein the lower gate (Gb) of the first transistor (T1) is directly connected to the anode of the display element (OLED).
  2. The display apparatus of claim 1, wherein the first voltage level (V LEVEL 1) is less than the second voltage level (V LEVEL 2).
  3. The display apparatus of claim 1, wherein each pixel further comprises: a seventh transistor (T3) configured to be turned on during the data writing period to connect the upper gate (Ga) and the drain (D) of the first transistor (T1) to each other; and a sixth transistor (T4) configured to be turned on during the first initialization period to transmit a reference voltage (VREF) to the upper gate (Ga) of the first transistor (T1).
  4. The display apparatus of any one of the preceding claims, wherein the storage capacitor (Cst) comprises a first electrode (CE1) connected to the upper gate (Ga) of the first transistor (T1) and a second electrode (CE2) connected to the anode of the display element (OLED).
  5. The display apparatus of any one of the preceding claims, wherein the first transistor (T1) comprises an n-type metal-oxide-semiconductor field-effect transistor (MOSFET).
  6. The display apparatus of any one of the preceding claims, wherein the first transistor (T1) comprises a lower gate electrode (GEb) operating as the lower gate (Gb), a semiconductor layer (Act) on the lower gate electrode (GEb), and an upper gate electrode (GEa) arranged on the semiconductor layer (Act) and operating as the upper gate (Ga).
  7. The display apparatus of claim 6, wherein the semiconductor layer (Act) comprises an oxide semiconductor material.
  8. The display apparatus of claim 1, wherein each of the pixels further comprise a seventh transistor (T3) connected between the upper gate (Ga) of the first transistor (T1) and the drain (D) of the first transistor (T1), and wherein the second transistor (T2) is connected between the data line and the source (S) of the first transistor (T1).
  9. The display apparatus of claims 8, wherein the same emission control signal is applied to a gate of the third transistor (T5) and a gate of the fourth transistor (T6) and/or wherein the second electrode (CE2) of the storage capacitor (Cst) is connected to the anode of the display element (OLED).
  10. The display apparatus of claims 8 or 9, wherein the first transistor (T1), the second transistor (T2), a sixth transistor (T4), the third transistor (T5), the fourth transistor (T6), and the fifth transistor (T7) are NMOS transistors.

Description

BACKGROUND FIELD Embodiments of the invention relate to a display apparatus including a display unit. DISCUSSION OF THE BACKGROUND A display apparatus visually displays data. A display apparatus may be used as a display of a small-sized product such as a mobile phone, or may be used as a display of a large-sized product such as a television. A display apparatus includes a plurality of pixels receiving electrical signals to emit light to display an image to the outside. Each of the plurality of pixels includes a display element, for example, an organic light-emitting diode in the case of an organic light-emitting display apparatus. Generally, an organic light-emitting display apparatus includes a thin-film transistor and an organic light-emitting diode on a substrate, and the organic light-emitting diode operates by emitting light by itself. Recently, as the use of display apparatuses has been diversified, various designs have been attempted to improve the quality of the display apparatuses. Examples of relevant display apparatuses in the prior art are disclosed in, for example, documents US 2021/272521 A1, US 2012/169798 A1, US 2022/122522 A1, US 2016/351122 A1, US 2020/357337 A1 and US 2018/158406 A1. The above information disclosed in this Background section is only for understanding of the background of the inventive concepts, and, therefore, it may contain information that does not constitute prior art. SUMMARY The invention is set out in the appended set of claims. One or more embodiments of the invention provide display apparatuses comprising a pixel capable of adjusting a threshold voltage of a driving transistor. Additional features of the inventive concepts will be set forth in the description which follows. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate illustrative embodiments of the invention, and together with the description serve to explain the inventive concepts. FIG. 1 is a schematic block diagram of a display apparatus according to an embodiment.FIG. 2 is an equivalent circuit diagram of a pixel not according to the invention and present for illustration purposes only.FIG. 3 shows an example of a timing diagram of control signals for operating a pixel circuit shown in FIG. 2 and a waveform of a lower gate-source voltage of a driving transistor.FIG. 4 is a cross-sectional view schematically illustrating a driving transistor according to an embodiment.FIG. 5 is an equivalent circuit diagram of a pixel not according to the invention and present for illustration purposes only.FIG. 6 is an equivalent circuit diagram of a pixel according to an embodiment.FIG. 7 is an equivalent circuit diagram of a pixel not according to the invention and present for illustration purposes only.FIG. 8 is an equivalent circuit diagram of a pixel not according to the invention and present for illustration purposes only. DETAILED DESCRIPTION Unless otherwise specified, the illustrated embodiments are to be understood as providing illustrative features of varying detail of some ways in which the inventive concepts may be implemented in practice. The use of cross-hatching and/or shading in the accompanying drawings is generally provided to clarify boundaries between adjacent elements. As such, neither the presence nor the absence of cross-hatching or shading conveys or indicates any preference or requirement for particular materials, material properties, dimensions, proportions, commonalities between illustrated elements, and/or any other characteristic, attribute, property, etc., of the elements, unless specified. Further, in the accompanying drawings, the size and relative sizes of elements may be exaggerated for clarity and/or descriptive purposes. When an embodiment may be implemented differently, a specific process order may be performed differently from the described order. For example, two consecutively described processes may be performed substantially at the same time or performed in an order opposite to the described order. Also, like reference numerals denote like elements. When an element, such as a layer, is referred to as being "on," "connected to," or "coupled to" another element or layer, it may be directly on, connected to, or coupled to the other element or layer or intervening elements or layers may be present. When, however, an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. To this end, the term "connected" may refer to physical, electrical, and/or fluid connection, with or without intervening elements. Further, the D1-axis, the D2-axis, and the D3-axis are not limited to three axes of a rectangular coordinate system, such as the x, y, and z - axes, and may be interpreted in a broader sense. For examp