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EP-4170718-B1 - DISPLAY PANEL AND ELECTRONIC DEVICE INCLUDING SAME

EP4170718B1EP 4170718 B1EP4170718 B1EP 4170718B1EP-4170718-B1

Inventors

  • SON, KI MIN
  • NOH, SEOK
  • PARK, KI BOK
  • HONG, YE WON

Dates

Publication Date
20260506
Application Date
20220822

Claims (16)

  1. A display panel (100) comprising: a substrate (10, SUBS) a circuit layer (12) disposed on the substrate (10, SUBS) and including a plurality of transistors; a light emitting element layer (14) disposed on the circuit layer (12) and including a plurality of light emitting elements (EL); and an encapsulation layer (16) configured to cover the light emitting element layer (14), wherein the circuit layer (12) includes at least a first transistor (TFT1) and a second transistor (TFT2), wherein the first transistor (TFT1) includes: a first oxide semiconductor pattern (ACT1), a gate electrode (GE1) overlapping the first oxide semiconductor pattern (ACT1) above the first oxide semiconductor pattern (ACT1), a first electrode (DE1) in contact with one side of the first oxide semiconductor pattern (ACT1) on the first oxide semiconductor pattern (ACT1), a second electrode (SE1) in contact with the other side of the first oxide semiconductor pattern (ACT1) on the first oxide semiconductor pattern (ACT1), and a first-first metal pattern disposed on the substrate (10) to overlap the first oxide semiconductor pattern (ACT1), and the second transistor (TFT2) includes: a second oxide semiconductor pattern (ACT2), a gate electrode (GE2) overlapping the second oxide semiconductor pattern (ACT2) above the second oxide semiconductor pattern (ACT2), a first electrode (DE2) in contact with one side of the second oxide semiconductor pattern (ACT2), a second electrode (SE2) in contact with the other side of the second oxide semiconductor pattern (ACT2), a first-second metal pattern disposed on the substrate (10) to overlap the second oxide semiconductor pattern (ACT2), and a second metal pattern (LS2) disposed between the second oxide semiconductor pattern (ACT2) and the first-second metal pattern, wherein the first electrode (DE1) and the second electrode (SE1) of the first transistor (TFT1) do not overlap with the first-second metal pattern in a cross-sectional view, and wherein the second electrode (SE1) of the first transistor (TFT1) extends towards the substrate (10, SUBS) and contacts the first-first metal pattern, and the second electrode (SE2) of the second transistor (TFT2) contacts the second metal pattern (LS2).
  2. The display panel (100) of claim 1, wherein all transistors in the circuit layer (12) are n-channel oxide transistors.
  3. The display panel (100) of claim 1 or 2, wherein the first-first metal pattern is disposed under the first oxide semiconductor pattern (ACT1), and the first-second metal pattern is disposed under the second oxide semiconductor pattern (ACT2).
  4. The display panel (100) of any of claims 1 to 3, further comprising: a fifth metal layer disposed above the first and second transistors (TFT1, TFT2), wherein the fifth metal layer includes: a fifth-first metal pattern (SD21) disposed on the first transistor (TFT1); a fifth-second metal pattern (SD22) disposed on the second transistor (TFT2); and a fifth-third metal pattern (SD23) configured to connect an anode electrode (AN0) of a light emitting element (EL) of the plurality of light emitting elements (EL) to the second electrode (SE2) of the second transistor (TFT2).
  5. The display panel (100) of claim 4, wherein the fifth metal layer includes titanium, and/or wherein the first and second electrodes (DE1, SE1; DE2, SE2) of the first and second transistors (TFT1, TFT2) include titanium.
  6. The display panel (100) of claim 4 or 5, further comprising: a first insulating layer (BUF1) disposed on the substrate (10, SUBS) to cover the first-first and first-second metal patterns; a second insulating layer (BUF2) disposed on the first insulating layer (BUF1) to cover the second metal pattern (LS2) and the first insulating layer (BUF 1); a third insulating layer (GI) disposed on the second insulating layer (BUF2) to cover the first and second oxide semiconductor patterns (ACT1, ACT2) and the second insulating layer (BUF2); a fourth insulating layer (ILD) disposed on the third insulating layer (GI) to cover the gate electrodes (GE1, GE2) of the first and second transistors (TFT1, TFT2) and the third insulating layer (GI); a fifth insulating layer (PAC1) disposed on the fourth insulating layer (ILD) to cover the first and second electrodes (DE1, SE1; DE2, SE2) of the first and second transistors (TFT1, TFT2) and the fourth insulating layer (ILD); and a sixth insulating layer (PAC2) disposed on the fifth insulating layer (PAC1) to cover the fifth metal layer and the fifth insulating layer (PAC1), wherein each of the first to fourth insulating layers (BUF1, BUF2, GI, ILD) is an inorganic film, and each of the fifth and sixth insulating layers (PAC1, PAC2) is an organic film having a thickness greater than that of each of the first to fourth insulating layers (BUF1, BUF2, GI, ILD), wherein, preferably, the first insulating layer (BUF1) has a thickness of 500 Å to 3000 Å.
  7. The display panel (100) of claim 6, further comprising: a jumping pattern (CE) disposed on the same layer as that of the first and second electrodes (DE1, SE1; DE2, SE2) of the first and second transistors (TFT1, TFT2), and configured to be in contact with a conductive semiconductor pattern (MACT) through a contact hole penetrating the third and fourth insulating layers (GI, ILD), and to be in contact with the first-second metal pattern through a contact hole penetrating the first to fourth insulating layers (BUF1, BUF2, GI, ILD).
  8. The display panel (100) of any of claims 1 to 7, wherein the circuit layer (12) includes: pixels (101) connected to data lines (102) through which a data voltage is applied, gate lines (103) through which a gate pulse is applied, and power lines through which a constant voltage is applied; and a gate driver (120) configured to generate the gate pulse, wherein each of the pixels (101) includes a pixel circuit, wherein the pixel circuit includes: a driving element (DT) configured to drive the light emitting element (EL); and a switch element (T01, T02, T03, T04) configured to be turned on/off in response to the gate pulse, wherein the gate driver (120) includes a plurality of transistors, and wherein the driving element (DT), the switch element (T01, T02, T03, T04), and the transistors of the gate driver (120), are n-channel oxide transistors.
  9. The display panel (100) of claim 8 wherein the switch element (T01, T02, T03, T04) has the same stacked structure as that of the first transistor (TFT1), and/or wherein the driving element (DT) has the same stacked structure as that of the second transistor (TFT2).
  10. The display panel (100) of claim 8 or 9, wherein at least a part of the gate driver (120) is disposed in a bezel area (BZ) outside a pixel array (AAA) in which the pixels (101) are arranged in the display panel (100), and wherein the circuit layer (12) further includes: a plurality of VSS lines (38) disposed in the pixel array and through which a pixel reference voltage (EVSS) is applied; and a shorting bar (34, 36) configured to connect the VSS lines (38).
  11. The display panel (100) of claim 10, wherein the circuit layer (12) further includes: a closed-loop electrostatic discharge wire (40) disposed in the bezel area (BZ); a plurality of electrostatic discharge elements (42) connected between the data lines (102) and the electrostatic discharge wire (40); and a plurality of electrostatic discharge elements (42) connected between the gate lines (103) and the electrostatic discharge wire (40), and wherein the electrostatic discharge elements (42) have the same stacked structure as that of the first transistor (TFT1).
  12. The display panel (100) of any of claim 8 to 11, wherein the circuit layer (12) further includes a demultiplexer connected to the data lines (102), and switch elements of the demultiplexer have the same stacked structure as that of the first transistor (TFT1).
  13. The display panel (100) of any of claims 1 to 12, wherein the circuit layer (12) includes a gate driver (120) including a shift register, each of signal transmitters (ST(n-1), ST(n), ST(n+1), ST(n+2)) in the shift register includes: a first control node (Q), a second control node (QB), and a control circuit configured to charge and discharge the first and second control nodes (Q, QB) in response to input signals; and a buffer (BUF) configured to output a gate pulse to a first output node and to output a carry pulse to a second output node, and wherein at least one of the control circuit and the buffer (BUF) includes at least two or more transistors having different cross-sectional structures.
  14. The display panel (100) of claim 13, wherein the control circuit includes: a transistor (T8) including a gate electrode connected to the second control node (QB), a first electrode connected to the first control node (Q), and a second electrode connected to a first buffer node (Qh); and a transistor (T9) including a gate electrode connected to the second control node (QB), a first electrode connected to the first buffer node (Qh), and a second electrode connected to a VSS node (GVSS2).
  15. The display panel (100) of claim 13 or 14, wherein each of the signal transmitters (ST(n-1), ST(n), ST(n+1), ST(n+2)) further includes: an inverter circuit (INV) configured to cause the second control node (QB) to discharge when the first control node (Q) is charged and to cause the second control node (QB) to charge when the first control node (Q) is discharged, and wherein the inverter circuit (INV) includes: a transistor (T11) including a gate electrode connected to a second buffer node (NET1), a first electrode connected to a VDD node (GVDD), and a second electrode connected to the second control node (QB); a transistor (T12) including a gate electrode and a first electrode connected to the VDD node (GVDD), and a second electrode connected to the second buffer node (NET1); a transistor (T13) including a gate electrode connected to the first control node (Q), a first electrode connected to the second buffer node (NET1), and a second electrode connected to a second VSS node (GVSS1); and a transistor (T14) including a gate electrode connected to the first control node (Q), a first electrode connected to the second control node (QB), and a second electrode connected to a first VSS node (GVSS2).
  16. The display panel (100) of any of claims 13 to 15, wherein the control circuit includes: a transistor (T51) including a gate electrode to which a line selection pulse (LSP) is applied, a first electrode to which an input signal (C(N-2)) is applied, and a second electrode connected to a first node (M); a capacitor (C3) coupled between the first node (M) and a VSS node (GVSS2); a transistor (T52) including a gate electrode connected to the first node (M), a first electrode connected to a VDD node (GVDD), and a second electrode connected to a second node (N1); a transistor (T53) including a gate electrode to which a reset pulse (RST) is applied, a first electrode connected to the second node (N1), and a second electrode connected to the first control node (Q); and a transistor (T54) including a gate electrode to which a start pulse (VST) is applied, a first electrode connected to the first control node (Q), and a second electrode connected to the VSS node (GVSS2).

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims priority to and the benefit of Korean Patent Application No. 10-2021-0117694, filed on September 03, 2021, Korean Patent Application No. 10-2021-0188351, filed on December 27, 2021, and Korean Patent Application No. 10-2022-0088215, filed on July 18, 2022. BACKGROUND 1. Field The present disclosure relates to a display panel and an electronic device including the same. 2. Discussion of Related Art An electroluminescence display device may be divided into an inorganic light emitting display device and an organic light emitting display device according to the material of the emission layer. The active matrix type organic light emitting display device includes an organic light emitting diode (hereinafter, referred to as "OLED") that emits light by itself, and has the advantage of fast response speed, high light-emitting efficiency, high luminance and wide viewing angle. In the organic light emitting display device, the OLED (Organic Light Emitting Diode) is formed in each pixel. The organic light emitting display device has a fast response speed, excellent light-emitting efficiency, luminance, and viewing angle, and has also excellent contrast ratio and color reproducibility because black gray scale can be expressed as complete black. The organic light emitting display device is used to reproduce video contents or visually display information in various electronic devices such as a television (TV) system, a tablet computer, a laptop computer, a navigation system, and a vehicle system as well as small/portable terminals such as a wearable device and a smart phone. A display panel of the organic light emitting display device includes a pixel circuit, and many transistors constituting a driving circuit for driving the pixel circuit. In order to reduce the number of manufacturing processes of the display panel, the transistors formed in the display panel are generally manufactured to have the same structure. As a result, the transistors formed in the display panel may cause unnecessary power consumption and may unnecessarily increase in size. An exemplary display panel is known from US 2017/278916 A1. SUMMARY An object of the present disclosure is to solve the above-mentioned necessity and/or problems. The present disclosure provides a display panel and an electronic device including the same, capable of improving power consumption, reducing a bezel area of the display panel, and improving image quality by optimizing a subthreshold slope factor (S-factor) of transistors depending on their use. The problems of the present disclosure are not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description. In an aspect of the present disclosure, a display panel according to claim 1 is provided. Further embodiments are described in the dependent claims. According to the present invention, a display panel defined in claim 1 is provided. Exemplary embodiments are defined in the dependent claims. A display panel according to an aspect of the present disclosure may include: a circuit layer disposed on a substrate and including a plurality of transistors; a light emitting element layer disposed on the circuit layer and including a plurality of light emitting elements; and an encapsulation layer configured to cover the light emitting element layer. All transistors in the circuit layer may be n-channel oxide transistors. The circuit layer may include at least a first transistor and a second transistor. The first transistor may include a first oxide semiconductor pattern, a gate electrode overlapping the first oxide semiconductor pattern above the first oxide semiconductor pattern, a first electrode in contact with one side of the first oxide semiconductor pattern on the first oxide semiconductor pattern, a second electrode in contact with the other side of the first oxide semiconductor pattern on the first oxide semiconductor pattern, and a first-first metal pattern disposed on the substrate to overlap the first oxide semiconductor pattern. The second transistor may include a second oxide semiconductor pattern, a gate electrode overlapping the second oxide semiconductor pattern above the second oxide semiconductor pattern, a first electrode in contact with one side of the second oxide semiconductor pattern on the second oxide semiconductor pattern, a second electrode in contact with the other side of the second oxide semiconductor pattern on the second oxide semiconductor pattern, a first-second metal pattern disposed on the substrate to overlap the second oxide semiconductor pattern, and a second metal pattern disposed between the second oxide semiconductor pattern and the first-second metal pattern. The first-first metal pattern may be disposed under the first oxide semiconductor pattern, and the first-second metal pattern may be disposed under the second oxide semiconducto