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EP-4170725-B1 - DISPLAY PANEL AND DISPLAY DEVICE

EP4170725B1EP 4170725 B1EP4170725 B1EP 4170725B1EP-4170725-B1

Inventors

  • LI, YAN
  • WU, Tsangchih

Dates

Publication Date
20260506
Application Date
20220330

Claims (12)

  1. A display panel (00), comprising: a substrate (01); and a first power line (VDD), a second power line (VSS) and a plurality of pixels (02) all located on one side of the substrate (01); wherein each of the pixels (02) is coupled to the second power line (VSS) and the first power line (VDD) respectively, and is configured to emit light under driving of a first voltage supplied by the first power line (VDD) and a second voltage supplied by the second power line (VSS); wherein, the first power line (VDD) and the second power line (VSS) each comprise: at least two metal layers (03) successively stacked along a direction away from the substrate (01), and a first insulating layer (04) located between each two adjacent metal layers (03) of the at least two metal layers, wherein each two adjacent metal layers (03) are coupled through a via hole (k0) passing through the first insulating layer (04), and an orthographic projection of a target metal layer (03) of the at least two metal layers (03) on the substrate (01) covers orthographic projections of the metal layers (03) excluding the target metal layer (03) of the at least two metal layers on the substrate (01); wherein, the metal layers (03) comprised in the first power line (VDD) are located on the same layers as source-drain metal layers comprised in the pixel (02), respectively, and the metal layers (03) comprised in the second power line (VSS) are located on the same layers as the respective source-drain metal layers comprised in the pixel (02), respectively; and the display panel (00) further comprises a connection electrode (05) and a second insulating layer (06), wherein the connection electrode (05) and a first pole of a light-emitting element (022) comprised in the pixel are located on a same layer, and the connection electrode (05) is coupled to the second pole of the light-emitting element (021), the second insulating layer (06) is located between the connection electrode (05) and the at least two metal layers (03); for the at least two metal layers (03) comprised in the second power line (VSS), a metal layer (03) close to the connection electrode (05) is coupled to the connection electrode (05) through a via hole (k1) passing through the second insulating layer (06).
  2. The display panel (00) according to claim 1, wherein the target metal layer (03) is located on one side of another metal layer (03), and the one side of another metal layer (03) is away from the substrate (01).
  3. The display panel (00) according to claim 1 or 2, wherein a number of the metal layers (03) comprised in the first power line (VDD) is the same as a number of the metal layers (03) comprised in the second power line (VSS).
  4. The display panel (00) according to claim 3, wherein the first power line (VDD) and the second power line (VSS) each comprises two metal layers (03).
  5. The display panel (00) according to claim 4, wherein each of the pixels (02) comprise an active layer (P1), a first gate metal layer (GATE1), a second gate metal layer (GATE2), a first source-drain metal layer (SD1) and a second source-drain metal layer (SD2) successively stacked along a direction away from the substrate (01); wherein the two metal layers (03) comprised in the first power line (VDD) are respectively located on same layers as the first source-drain metal layer (SD1) and the second source-drain metal layer (SD2); and the two metal layers (03) comprised in the second power line (VSS) are respectively located on same layers as the first source-drain metal layer (SD1) and the second source-drain metal layer (SD2).
  6. The display panel (00) according to any one of claims 1 to 5, wherein a number of the metal layers (03) comprised in the second power line (VSS) is greater than a number of the metal layers (03) comprised in the first power line (VDD).
  7. The display panel (00) according to claim 6, wherein the first power line (VDD) comprises two layers of the metal layer (03); the second power line (VSS) comprises three layers of the metal layer (03).
  8. The display panel (00) according to claim 7, wherein each of the pixels (02) comprise an active layer (P1), a first gate metal layer (GATE1), a second gate metal layer (GATE1), a first source-drain metal layer (SD1), a second source-drain metal layer (SD2) and a third source-drain metal layer (SD3) successively stacked along a direction away from the substrate (01); wherein the two metal layers (03) comprised in the first power line (VDD) are respectively located on same layers as the first source-drain metal layer (SD1) and the second source-drain metal layer (SD2); the three metal layers (03) comprised in the second power line (VSS) are respectively located on same layers as the first source-drain metal layer (SD1), the second source-drain metal layer (SD2) and the third source-drain metal layer (SD3).
  9. The display panel (00) according to claim 8, further comprising: a data line (D1) located on the one side of the substrate (01), and each pixel (02) is coupled to the data line (D1) and used to emit light under driving of the first voltage, the second voltage and a data signal supplied by the data line (D1); wherein the data line (D1) is located on a same layer as the third source-drain metal layer (SD3).
  10. The display panel (00) according to any one of claims 1 to 9, wherein each pixel (02) comprises a pixel circuit (021) and a light-emitting element (022), wherein the pixel circuit (021) is respectively coupled to the first power line (VDD) and a first pole of the light-emitting element (022), a second pole of the light-emitting element (022) is coupled to the second power line (VSS), and the first pole and the second pole of the light-emitting element (022) are successively arranged along a direction away from the at least two metal layers (03).
  11. The display panel (00) according to any one of claims 1 to 10, wherein the display panel (00) is a flexible organic light-emitting diode, OLED, display panel.
  12. The display panel (00) according to any one of claims 1 to 11, wherein the substrate (01) has a display region (A1) and a peripheral region (A2) surrounding the display region (A1); wherein the first power line (VDD) is located in the display region (A1), and the second power line (VSS) is located in the peripheral region (A2).

Description

FIELD The present disclosure relates to the field of display technologies, and more particularly to a display panel and a display device. BACKGROUND Organic light-emitting diode (OLED) display panels are widely applied for various display devices due to advantages of self light-emitting, small thickness, light weight and high light-emitting efficiency. In the related art, an OLED display panel generally includes a plurality of pixels. Each pixel is coupled to a first power line (ie, VDD line) and a second power line (ie, VSS line), respectively, and may emit light under driving of a first voltage supplied by the first power line and a second voltage supplied by the second power line. However, the OLED display panels in the related art have relatively high power consumption and high loss during operation. KR20080104875A discloses an organic light emitting display. US2021/183991A1 discloses a transparent display panel and a transparent display device. US2021/074792A1 discloses a display panel, a method of manufacturing the display panel, and a display device. SUMMARY The invention is defined by the appended claims. The present disclosure provides a display panel and a display device, capable of addressing deficiencies of relatively high power consumption and high loss during operation of the display panel in the related art. The technical solution is as follows: According to a first aspect, the present invention provides a display panel. The display panel includes: a substrate; anda first power line, a second power line and a plurality of pixels all located on one side of the substrate; in which each of the pixels is coupled to the second power line and the first power line respectively, and is configured to emit light under driving of a first voltage supplied by the first power line and a second voltage supplied by the second power line;in which, the first power line and the second power line each includes: at least two metal layers successively stacked along a direction away from the substrate, and a first insulating layer located between each two adjacent metal layers of the at least two metal layers, in which each two adjacent metal layers are coupled through a via hole passing through the first insulating layer, and an orthographic projection of a target metal layer of the at least two metal layers on the substrate covers orthographic projections of the metal layers excluding the target metal layer of the at least two metal layers on the substrate; wherein the metal layers comprised in the first power line are located on a same layer as source-drain metal layers comprised in pixels, respectively, and the metal layers comprised in the second power line are located on a same layer as respective source-drain metal layers comprised in pixels, respectively; and the display panel further comprises a connection electrode and a second insulating layer, wherein the connection electrode and a first pole of a light-emitting element comprised in the pixel are located on a same layer, and the connection electrode is coupled to the second pole of the light-emitting element, the second insulating layer is located between the connection electrode and the at least two metal layers; for the at least two metal layers comprised in the second power line, a metal layer close to the connection electrode is coupled to the connection electrode through a via hole passing through the second insulating layer. In an embodiment, the target metal layer is located on one side of another metal layer, and the one side of another metal layer is away from the substrate. In an embodiment, a number of the metal layers included in the first power line is the same as a number of the metal layers included in the second power line. In an embodiment, the first power line and the second power line each includes two metal layers. In an embodiment, the pixel includes an active layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer and a second source-drain metal layer successively stacked along a direction away from the substrate; in which the two metal layers included in the first power line are respectively located on same layers as the first source-drain metal layer and the second source-drain metal layer; andthe two metal layers included in the second power line are respectively located on same layers as the first source-drain metal layer and the second source-drain metal layer. In an embodiment, a number of the metal layers included in the second power line is greater than a number of the metal layers included in the first power line. In an embodiment, the first power line includes two layers of the metal layer; the second power line includes three layers of the metal layer. In an embodiment, the pixel includes an active layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer and a third source-drain metal layer successively stacked alo