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EP-4170909-B1 - SUB-SAMPLING PHASE LOCKED LOOP WITH COMPENSATED LOOP BANDWIDTH AND INTEGRATED CIRCUIT INCLUDING THE SAME

EP4170909B1EP 4170909 B1EP4170909 B1EP 4170909B1EP-4170909-B1

Inventors

  • Kim, Gyusik
  • KIM, SEUNGJIN
  • OH, Seunghyun

Dates

Publication Date
20260513
Application Date
20221011

Claims (14)

  1. A sub-sampling phase locked loop (100) comprising: a slope generating and sampling circuit (200) comprising a resistor (RS) and a capacitor (CS1, CS2) and configured to generate a sampling voltage based on a reference clock signal and an output clock signal, wherein a slope of the sampling voltage is inversely proportional to a resistance of the resistor (RS) and a capacitance of the capacitor (CS1, CS2); a first transconductance circuit (300) configured to generate a first output control voltage based on the sampling voltage, a reference voltage, and a control which is inversely proportional with an equivalent resistance of the switched capacitor resistor (520) such that an influence of PVT variation on the loop bandwidth is compensated; a second transconductance circuit (400) configured to generate a second output control voltage based on the sampling voltage, the reference voltage, and the control current; a constant transconductance bias circuit (500) including a switched capacitor resistor (520), the constant transconductance bias circuit (500) being configured to generate the control current; a loop filter (600) connected to an output terminal of the first transconductance circuit (300) and an output terminal of the second transconductance circuit (400), the loop filter (600) including a first resistor (RLF) connected between an output terminal of the first transconductance circuit (300) and a ground voltage; and a voltage controlled oscillator (700) configured to generate the output clock signal based on the first output control voltage and the second output control voltage, wherein a proportional path of the sub-sampling phase locked loop (100) is formed by the first transconductance circuit (300) and the first resistor; and an integral path of the sub-sampling phase locked loop (100) is formed by the second transconductance circuit (400).
  2. The sub-sampling phase locked loop (100) of claim 1, wherein the constant transconductance bias circuit (500) further includes: a first circuit (510) connected between a power supply voltage and the ground voltage; and a second circuit (530) connected to the power supply voltage and the first circuit (210), and configured to output the control current, and the switched capacitor resistor (520) is connected between the first circuit (510) and the ground voltage and the switched capacitor resistor (520) is configured to operate based on a first phase signal and a second phase signal.
  3. The sub-sampling phase locked loop (100) of claim 2, wherein the switched capacitor resistor (520) includes: a first switch connected between a first node and a second node, the first switch being configured to be turned on and off based on the first phase signal, the first node being connected to the first circuit (510); a first capacitor connected between the second node and the ground voltage; and a second switch connected in parallel with the first capacitor between the second node and the ground voltage, the second switch configured to be turned on and off based on the second phase signal.
  4. The sub-sampling phase locked loop (100) of claim 3, wherein a current level of the control current generated by the constant transconductance bias circuit (500) is proportional to a capacitance of the first capacitor.
  5. The sub-sampling phase locked loop (100) of claim 3 or claim 4, wherein an active duration of the first phase signal and an active duration of the second phase signal do not overlap.
  6. The sub-sampling phase locked loop (100) of any of claims 3-5, wherein the first circuit (510) includes: a first transistor and a second transistor connected in series between the power supply voltage and the ground voltage; and a third transistor and a fourth transistor connected in series between the power supply voltage and the first node, and a gate electrode of the first transistor and a gate electrode of the third transistor are connected to each other, and a gate electrode of the second transistor and a gate electrode of the fourth transistor are connected to each other.
  7. The sub-sampling phase locked loop (100) of claim 6, wherein the second circuit (530) includes a fifth transistor connected between the power supply voltage and a third node, the third node outputting the control current, and a gate electrode of the fifth transistor is connected to the gate electrode of the first transistor and the gate electrode of the third transistor.
  8. The sub-sampling phase locked loop (100) of any of claims 3-7, wherein the loop filter (600) includes: a second capacitor connected between the output terminal of the second transconductance circuit (400) and the ground voltage.
  9. The sub-sampling phase locked loop (100) of claim 8, wherein a voltage level of the first output control voltage generated by the first transconductance circuit (300) is proportional to a resistance of the first resistor, and is proportional to a capacitance of the first capacitor.
  10. The sub-sampling phase locked loop of claim 1, wherein a loop bandwidth of the sub-sampling phase locked loop is proportional to a gain of the proportional path.
  11. The sub-sampling phase locked loop (100) of any preceding claim, wherein the first transconductance circuit includes a first input terminal, and a second input terminal, the first input terminal being configured to receive the sampling voltage, and the second input terminal being configured to receive the reference voltage, and the second transconductance circuit includes a third input terminal and a fourth input terminal, the third input terminal being configured to receive the reference voltage, and the fourth input terminal being configured to receive the sampling voltage.
  12. The sub-sampling phase locked loop of any preceding claim, wherein the first transconductance circuit and the second transconductance circuit have a same structure.
  13. The sub-sampling phase locked loop of any preceding claim, wherein the first transconductance circuit and the second transconductance circuit have different structures.
  14. An integrated circuit comprising: a sub-sampling phase locked loop according to any preceding claim; and an internal circuit configured to operate based on the output clock signal.

Description

BACKGROUND 1. Technical Field Example embodiments relate generally to semiconductor integrated circuits, and more particularly to sub-sampling phase locked loops (PLLs) with compensated loop bandwidth and/or integrated circuits including the sub-sampling phase locked loops. 2. Description of the Related Art In spite of improvements of speed and data transmission rates of peripheral devices (such as memory, communication devices, or graphic devices), operating speeds of peripheral devices have not kept up with operating speeds of processors, in some cases. Further, there is often a speed difference between new microprocessors and their peripheral devices. Thus, some high performance digital systems have been required or desired to dramatically improve speed of peripheral devices. For example, a load of a bus increases and a transmission frequency becomes faster in an input and output method of transmitting data by synchronizing a clock signal for a data transmission between a memory device and a memory controller. US 2019/214976 A1 discloses a PLL including a Gm circuit that converts the input voltage to current, an analog loop filter for filtering the signal received from the Gm circuit, a voltage controlled oscillator (VCO) for producing a frequency and a sampling phase detector (SPD). US 10 972 109 B2 discloses a sub-sampler phase locked loop (SSPLL) system having a frequency locking loop (FLL) and a phase locked loop (PLL) is disclosed. The FLL is configured to detect frequency variations between a phase locked loop (PLL) output signal and a reference frequency and automatically generate a pulsed correction signal upon the detected frequency variations and apply the pulsed correction signal to a voltage controlled oscillator (VCO) control voltage. The PLL is configured to generate the PLL output signal based on the VCO control voltage. US 7,583,166 B2 discloses an apparatus for enhancing Q factor of an inductor. The apparatus includes a negative resistance generator coupled to the inductor for providing a negative resistance, and a bias circuit coupled to the negative resistance generator for biasing the negative resistance generator. US 2015/177772 A1 discloses an electronic circuit with a self-calibrated PTAT current reference includes a PTAT current generator dependent on at least one integrated resistor for supplying a PTAT output current. It further includes a reference current generator dependent on at least one switched capacitor resistor, for supplying a reference current. The reference current and the PTAT output current are compared in a comparator so as to digitally adapt the programmable integrated resistor, or to digitally adapt the dimensional ratio of the transistors of a current mirror in the PTAT current generator, to supply the adapted PTAT output current. US 7,345,550 B2 discloses phase locked loop (PLL) with reduced loop filter components having dual charge pumps and corresponding dual signal paths that reduce on-chip component size within the filters. The dual paths are combined via dual varactors within a voltage controlled oscillator to further reduce loop filter components. EP 0,642,227 A1 discloses an oscillator for oscillating an electric signal, a comparator being electrically connected to the oscillator for fetching the electric signal from the oscillator and subsequent comparison in phase of an external input signal with the electric signal for generation of a detecting signal according to a result of the comparison, a charge-pump including first and second current sources being electrically connected in parallel to the comparator for fetching the detecting signal from the comparator and subsequent generation of first and second pump currents by the first and second current sources respectively on the basis of the detecting signal. WO 2018/140263 A1 discloses an apparatus for generating oscillating signals. The apparatus includes a phase-locked loop (PLL) having a first switch coupled to a sampling input node of the PLL, an integrator coupled to an output of the sampling circuit, and a voltage-controlled oscillator (VCO) having an input coupled to an output of the integrator. In certain aspects, the PLL may also include a feedback path coupled to an output of the VCO and a control input of the first switch. SUMMARY At least one example embodiment of the present disclosure provides a sub-sampling phase locked loop (PLL) with loop bandwidth compensated for influences of process, voltage, and temperature (PVT) variations. At least one example embodiment of the present disclosure provides an integrated circuit including the sub-sampling phase locked loop. According to the invention there is provided a sub-sampling phase locked loop (PLL) according to claim 1. According to some example embodiments, there is provided an integrated circuit according to claim 14. According to some example embodiments, a sub-sampling phase locked loop (PLL) includes a slope generating and sampling cir