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EP-4177953-B1 - IMAGE SENSOR INCLUDING A BURIED GATE

EP4177953B1EP 4177953 B1EP4177953 B1EP 4177953B1EP-4177953-B1

Inventors

  • CHOI, HYUKSOON
  • AHN, Daekun

Dates

Publication Date
20260506
Application Date
20221109

Claims (14)

  1. An autofocus image sensor (300) comprising a plurality of pixels (PX), the image sensor comprising a semiconductor substrate (SUB1) including a first surface and a second surface, the semiconductor substrate having photoelectric conversion regions (PD) disposed therein, wherein each said pixel comprises; a first said photoelectric conversion region (PD_L) and a second said photoelectric conversion region (PD_R) spaced apart from the first photoelectric conversion region; a floating diffusion region (FD) disposed within the semiconductor substrate, the floating diffusion region being adjacent to the first surface; and a buried gate structure (150) disposed within a buried gate trench that extends from the first surface of the semiconductor substrate towards an interior of the semiconductor substrate, the buried gate structure comprising: a first buried gate electrode (TG_L) disposed within a first buried gate trench (150T) that is adjacent to a first side part of the floating diffusion region, and a second buried gate electrode (TG_R) disposed within a second buried gate trench (150T) that is spaced apart from the first buried gate trench (150T) and is adjacent to a second side part of the floating diffusion region that is opposite to the first side part, wherein the first photoelectric conversion region (PD_L) at least partially overlaps the first buried gate electrode (TG_L), and the second photoelectric conversion region (PD_R) at least partially overlaps the second buried gate electrode (TG_R). characterised in that , in a plan view, the floating diffusion region (FD) has a circular horizontal cross-section, the first buried gate electrode (TG_L) has a semi-circular horizontal cross-section and surrounds at least a part of the floating diffusion region, and the second buried gate electrode (TG_R) has a semi-circular horizontal cross-section and surrounds at least another part of the floating diffusion region.
  2. The image sensor of claim 1, wherein the first buried gate electrode and the second buried gate electrode collectively surround a periphery of the floating diffusion region.
  3. The image sensor (300) of any preceding claim, wherein the first buried gate electrode comprises: a first side wall (TG_S1) facing the first side part of the floating diffusion region; and a second side wall (TG_S2) opposite to the first side wall, wherein the second buried gate electrode comprises: a third side wall (TG_S3) facing the second side part of the floating diffusion region; and a fourth side wall (TG_S4) opposite to the third side wall, wherein the first side wall and the third side wall oppose each other, and wherein the second side wall and the fourth side wall oppose each other.
  4. The image sensor (300) of claim 3, wherein the second side wall (TG_S1) and the fourth side wall (TG_S4) are mirror symmetrical with respect to each other, with the floating diffusion region disposed therebetween.
  5. The image sensor (300) of claim 3 or 4, wherein the first side wall (TG_S1) and the third side wall (TG_S3) are mirror symmetrical with respect to each other, with the floating diffusion region disposed therebetween.
  6. The image sensor (300) of any preceding claim, wherein the first buried gate electrode and the second buried gate electrode oppose each other.
  7. The image sensor (300) of claim 6, wherein the first buried gate electrode (TG_L) and the second buried gate electrode (TG_R) are mirror symmetrical with respect to each other.
  8. The image sensor (300) of any preceding claim, wherein the first buried gate electrode and the second buried gate electrode have upper surfaces at a higher level than a level of the first surface of the semiconductor substrate, and the first buried gate electrode and the second buried gate electrode extend from the first surface towards an interior of the semiconductor substrate, wherein the higher level is defined with respect to a direction from the second surface of the semiconductor substrate towards the first surface of the semiconductor substrate.
  9. The image sensor (300) of any preceding claim, wherein the first buried gate electrode and the second buried gate electrode have upper surfaces at a lower level than a level of the first surface of the semiconductor substrate, and the image sensor further comprises a buried insulating layer (158) disposed on the first buried gate electrode and in an upper portion of the first buried gate trench and disposed on the second buried gate electrode and in an upper portion of the second buried gate trench, wherein the lower level is defined with respect to a direction from the first surface of the semiconductor substrate towards the second surface of the semiconductor substrate.
  10. The image sensor (300) of any preceding claim, comprising: a stack structure including a first substrate structure (SUB1) and a second substrate structure (SUB2) that is stacked upon the first substrate structure, an active pixel region in which the plurality of pixels are defined, and a pad region (PDR) disposed on at least one side of the active pixel region.
  11. The image sensor (300) of claim 10, wherein the first substrate structure comprises: the first semiconductor substrate including the first surface and the second surface, the first semiconductor substrate having the photoelectric conversion regions of a said pixel disposed therein, the pixel comprising: the first buried gate electrode having at least a part extending from the first surface of the first semiconductor substrate towards an interior of the first semiconductor substrate; the second buried gate electrode having at least a part extending from the first surface of the first semiconductor substrate towards an interior of the first semiconductor substrate, the second buried gate electrode being spaced apart from the first buried gate electrode; and the floating diffusion region disposed within the first semiconductor substrate and at least partially surrounded by the first buried gate electrode and the second buried gate electrode.
  12. The image sensor (300) of claim 10 or 11, wherein the second substrate structure comprises a logic circuit configured to drive the plurality of pixels.
  13. The image sensor (300) of any one of claims 10 to 12, wherein the first substrate structure further comprises a pixel transistor (RX, SX, DX) disposed on the first surface of the first semiconductor substrate, the pixel transistor being electrically connected to the plurality of pixels.
  14. Use of the image sensor (300) of any preceding claim to perform an autofocus function, the method comprising, in at least one said pixel,: the first buried gate electrode (TG_L) transferring charges stored in the first photoelectric conversion region (PD_L) to the floating diffusion region (FD); the second buried gate electrode (TG_R) transferring charges stored in the second photoelectric conversion region (PD_R) to the floating diffusion region (FD); and deriving phase difference information by sensing a difference value between the charges stored in the first photoelectric conversion region (PD_L) and the charges stored in the second photoelectric conversion region (PD_R).

Description

TECHNICAL FIELD The present invention relates to an image sensor, and more particularly, embodiments relate to an image sensor including a buried gate. BACKGROUND An image sensor converts an optical image signal into an electrical signal. An image sensor includes a plurality of pixels each receiving incident light and converting the incident light into an electrical signal using a photodiode region thereof. As the degree of integration of an image sensor increases, the size of each pixel becomes smaller, and accordingly, the charge transfer efficiency of each pixel decreases. Image sensors comprising buried gates according to the prior-art are as shown in documents WO 2020/054282 Aland US 2021/036039 A1. SUMMARY The image sensor of the present invention is as recited in claim 1. An image sensor includes a semiconductor substrate including a first surface and a second surface and having a photoelectric conversion region therein. A floating diffusion region is disposed within the semiconductor substrate. The floating diffusion region is adjacent to the first surface. A buried gate structure is disposed within a buried gate trench extending from the first surface of the semiconductor substrate towards an interior of the semiconductor substrate. The buried gate structure includes a first buried gate electrode disposed within a first buried gate trench that is adjacent to a first side part of the floating diffusion region. A second buried gate electrode is disposed within a second buried gate trench that is spaced apart from the first buried gate trench and adjacent to a second side part of the floating diffusion region that is opposite to the first side part. Preferred embodiments are defined by the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: FIG. 1 is a perspective view schematically illustrating an image sensor according to example embodiments;FIG. 2 is a magnified layout diagram of a part A of FIG. 1;FIG. 3 is a cross-sectional view taken along line B1-B1' of FIG. 2;FIG. 4 is a cross-sectional view taken along line B2-B2' of FIG. 2;FIG. 5 is a magnified view of a part CX1 of FIG. 3;FIG. 6 is a layout diagram schematically illustrating an arrangement of a floating diffusion region and a transfer gate corresponding to one pixel;FIG. 7 is an equivalent circuit diagram of pixels of an image sensor according to example embodiments;FIG. 8 is a plan view schematically illustrating an image sensor according to example embodiments;FIG. 9 is a cross-sectional view illustrating an image sensor according to example embodiments;FIG. 10 is a magnified view of a part CX1 of FIG. 9;FIG. 11 is a layout diagram schematically illustrating an image sensor according to example embodiments;FIG. 12 is a cross-sectional view taken along line B1-B1' of FIG. 11;FIG. 13 is a layout diagram schematically illustrating an arrangement of a floating diffusion region and a transfer gate corresponding to one pixel;FIG. 14 is a perspective view schematically illustrating an image sensor according to an example embodiment;FIG. 15 is a cross-sectional view taken along line B3-B3' of FIG. 14;FIG. 16 is a layout diagram illustrating a first substrate structure corresponding to one pixel of FIG. 14;FIG. 17 is a layout diagram illustrating a third substrate structure corresponding to one pixel of FIG. 14;FIG. 18 is a cross-sectional view illustrating an image sensor according to example embodiments;FIG. 19 is a layout diagram illustrating a first substrate structure corresponding to one pixel of FIG. 18;FIG. 20 is a layout diagram illustrating a third substrate structure corresponding to one pixel of FIG. 18; andFIG. 21 is a block diagram of an image sensor according to an example embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS Hereinafter, example embodiments of the inventive concept are described in detail with reference to the accompanying drawings. FIG. 1 is a perspective view schematically illustrating an image sensor 100 according to example embodiments. FIG. 2 is a magnified layout diagram of a part A of FIG. 1. FIG. 3 is a cross-sectional view taken along line B1-B1' ofFIG. 2. FIG. 4 is a cross-sectional view taken along line B2-B2' of FIG. 2. FIG. 5 is a magnified view of a part CX1 of FIG. 3. FIG. 6 is a layout diagram schematically illustrating an arrangement of a floating diffusion region FD and a transfer gate TG corresponding to one pixel PX. Referring to FIGS. 1 to 6, the image sensor 100 may be a stack-type image sensor including a stack structure ST1 in which a first substrate structure SUB1 and a second substrate structure SUB2 are stacked upon one another in a vertical (e.g., Z) direction. An active pixel region APR may be disposed at a center part of the stack structure ST1. A plurality of pixels PX may be disposed in the active pixel region APR. T