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EP-4181376-B1 - ADAPTIVE MINIMUM DUTY CYCLE DESIGN TO EXTEND OPERATIONAL VOLTAGE RANGE FOR DC/DC CONVERTERS

EP4181376B1EP 4181376 B1EP4181376 B1EP 4181376B1EP-4181376-B1

Inventors

  • Wenliang, Chen
  • Jiansong, Chen

Dates

Publication Date
20260513
Application Date
20221011

Claims (7)

  1. A controller for a switched mode power supply, SMPS (100), comprising: an error amplifier (121) configured to compare a sampled output voltage (122) of the SMPS with a first reference voltage (VR1) to generate an error voltage signal (VCT); an oscillator circuit (130) configured to provide a clock signal (VSET); an adaptive minimum duty cycle circuit (150) configured to receive the error voltage signal and to generate a current signal to vary an oscillating frequency of the clock signal in response to the error voltage signal; the adaptive minimum duty-cycle circuit comprising: a first PMOS transistor (PM1) with a gate node coupled to the error voltage signal; a first NMOS transistor (NM1) with a gate node coupled to a third reference voltage; a first resistor (R1); and a current mirror (151) having: a first branch (151-1) coupled to the first NMOS transistor, the first resistor, and the first PMOS transistor connected in series; and a second branch (151-2) providing a second current to the oscillator circuit at a node (136); the second current comprising the current signal; and a pulse width modulation, PWM, switching control circuit (124) configured to receive the error voltage signal and the clock signal and to provide a PWM switching control signal (127, 128) for controlling first and second power switches of the SMPS (114, 115); wherein: the oscillator circuit comprises: a capacitor (131); a first constant current source (133); a current mirror (134) coupled to the first constant current source at the node (136) to provide a first current for charging the capacitor; a comparator (OSC CMP) for comparing a voltage (VC) on the capacitor with a second reference voltage (VR2) for discharging the capacitor; and an inverter (137) coupled to an output of the comparator to provide the clock signal; the adaptive minimum duty-cycle circuit further comprises an adaptive minimum duty-cycle enabling circuit (153) configured to determine whether a minimum on-time condition is reached and, if so, provide an adaptive minimum duty-cycle enabling signal (EN_DMIN) that causes the current signal to be coupled to the oscillator circuit at the node (136) to vary a charging current of the capacitor to vary the oscillating frequency; and the adaptive minimum duty-cycle circuit further comprises a second current source (155), and the adaptive minimum duty-cycle enabling signal further is configured to cause the second current source (155) to be coupled to the oscillator circuit at the node (136) and to cause the first constant current source to be decoupled from the node (136) of the oscillator circuit when the minimum on-time condition is reached, wherein the second current source (155) is configured to compensate for temperature variations caused by the resistance of the first resistor (R1) and the turn-on threshold voltages of the first NMOS transistor (NM1) and the first PMOS transistor (PM1).
  2. The controller of claim 1, wherein the adaptive minimum duty-cycle enabling circuit (150)is further configured to determine that following conditions are met before providing the adaptive minimum duty-cycle enabling signal: soft-start completed; output voltage power good; and continuous conduction mode, CCM, or forced PWM mode.
  3. A switched mode power supply, SMPS (100), comprising: an input node (111) for coupling to an input voltage (VIN); an output node (112) for providing an output voltage (VOUT); a first switch (114) coupled between the input node and a switching node (113); a second switch (115) coupled between the switching node and ground node; an inductor (116) coupled between the switching node and the output node for providing an inductor current (I_IND) to the output node under control of the first and second switches in response to a switching control signal (127, 128); and a controller according to any preceding claim.
  4. The switched mode power supply of claim 3, wherein the PWM circuit comprises: a comparator (PWM CMP) configured to compare the error voltage signal and a saw-tooth signal (VSUM) and provide an output signal (125); a latch (126) configured to receive the output signal from the comparator and provide the switching control signal (127, 128) using pulse-width modulation to control the first and second switches; and a current sense circuit (106) including an amplifier (CSA), a transistor (107), and a resistor (108), the current sense circuit being configured to provide a signal.
  5. The switched mode power supply of any one of claims 3 or 4, wherein the switched mode power supply is configured as a buck converter.
  6. A method (400) for a switched mode power supply, SMPS, comprising: providing (410) an error voltage signal based on a difference between a sampled output voltage of the SMPS and a target voltage; generating (420), by an oscillator circuit (130), a clock signal characterized by an oscillating frequency; generating (450) a switching control signal based on the error voltage signal and the clock signal using pulse-width modulation, PWM; varying (440) the oscillating frequency of the clock signal according to the error voltage signal; and applying (460) the switching control signal to control the first and second power switches of the SMPS; wherein the method further comprises using an adaptive minimum duty-cycle circuit that includes: a first PMOS transistor with a gate node coupled to the error voltage signal; a first NMOS transistor with a gate node coupled to a third reference voltage; a first resistor; and a current mirror having: a first branch coupled to the first NMOS transistor, the first resistor, and the first PMOS transistor connected in series; and a second branch providing a second current to a node (136) of a current mirror (134) of the oscillator circuit wherein generating a clock signal comprises: using a first current from a first constant current source (133) coupled to the node (136) to charge a capacitor; and using a comparator for comparing a voltage on the capacitor with a second reference voltage to determine a condition for discharging the capacitor; and wherein varying the oscillating frequency comprises: generating the second current using the error voltage signal as an input; and using the second current to vary a charging current of the capacitor; the method further comprising determining (431) whether a minimum on-time condition is reached and, if so, providing an adaptive minimum duty-cycle enabling signal that causes the second current to be coupled to the oscillator circuit at the node (136); and wherein the adaptive minimum duty-cycle enabling signal further causes a second current source (155) to be coupled to the oscillator circuit at the node (136) and causes the first constant current source to be decoupled from the node (136) of the oscillator circuit when the minimum on-time condition is reached, wherein the second current source (155) is configured to compensate for temperature variations caused by the resistance of the first resistor (R1) and the turn-on threshold voltages of the first NMOS transistor (NM1) and the first PMOS transistor (PM1).
  7. The method of claim 6, wherein determining whether a minimum on-time condition is reached comprises comparing the divided input voltage with a threshold voltage, or comparing a measured on-time with a preset minimum on-time.

Description

BACKGROUND Switched-mode power supplies (SMPS), such as DCDC converters, are widely used in personal, automotive, and industrial electronics as DCDC power supplies, LED drivers, battery chargers and many other applications. In order to support the wide range of applications, the DCDC converters are required to cover a wide-range of input voltage (VIN) and output voltage (VOUT). It saves costs and time to market that the DCDC converters have the capability to handle a wide range of VIN and VOUT voltages without the need of multiple designs to cover only certain portions of the required operational voltage range. In switched-mode power supplies, the minimum duty cycle (D_min) or minimum on-time (Ton_min) is confined by logic delays and charging/discharging times associated with its output FETs, including propagation delays of controller logic, blanking time of a high-side sensing amplifier, required dead-times to avoid shoot-through current, and the driver's rise and fall times, etc. All these required delay times are needed to guarantee stable operation of the converters. If these timing requirements are not met, the converters can be susceptible to malfunction, instability, and, in the worst case, non-recoverable damages. Therefore, the physical requirements on D_min impose the limitations on VIN (or VOUT) operational range of switched-mode power supplies. The inventors have observed that these conventional solutions have many drawbacks. For example, some conventional designs reduce the minimum duty cycle (D_min) or minimum on-time (Ton_min) of buck converters by, for example, a) using process technology with lower supply voltages for shorter logic delays, b) using new topology for the high-side sensing amplifier with shorter blanking time, c) increasing the driver's strength for faster rise and fall times, or d) using complicated circuits similar to constant-on-time (COT) converters to address the issue, requiring valley and peak current detection and many more circuits. All these solutions have increased costs, increased compromises of converter's performance, or lead to the addition of complicated circuits. For example, costs can be increased due to the requirements of extra mask layers and process steps for faster digital logic with a lower supply voltage. Increasing the drivers' strength can cause worse electro-magnetic-emission (EMI) issues to prevent applications in certain systems. Thus, the trade-offs among operational voltage range, costs, and performance are compromised in the conventional solutions. Another conventional design reduces the duty cycle of a buck converter using a clock that lowers its oscillating frequency by a current that varies directly with the input voltage for the buck converter to operate at higher input voltages. However, its open-loop design considers mainly the variation of the input voltage. In embodiments of the invention, both the variation of the input and output voltages are taken into account along with an error voltage signal in a close-loop feedback system to provide accurate control for wider applications. US 2019/238054 A1 discloses a circuit including a power conversion circuit including an inductor and configured to convert an input voltage to an output voltage in accordance with at least one switching signal. The circuit further includes a first current sense circuit configured to generate a current sense signal that represents an inductor current, a voltage sense circuit configured to generate a voltage sense signal that represents the output voltage, and a switching controller including an error amplifier configured to generate an error signal representing the difference between a reference voltage and the voltage sense signal. The switching controller further includes an oscillator circuit configured to generate, for pulse frequency modulation (PFM) operation of the power conversion circuit, the switching signal as a sequence of pulses with a pulse repetition frequency that depends on the error signal and the current sense signal. US 2011/062932 A1 discloses a method of operating a DC/DC converter comprising adjusting the frequency of a pulse width modulation signal during current limit conditions as a function of both the input voltage and the output voltage of the DC/DC converter. US 2018/337601 A1 discloses a DC-DC converter and a method for maintaining an output voltage of the DC-DC converter, wherein the DC-DC converter is configured to operate in a discontinuous conduction mode, within a predetermined voltage range. The method comprises adjusting a duty cycle of the DC-DC converter based on the output voltage to maintain the output voltage within a predetermined voltage range; wherein the duty cycle of the DC-DC converter is adjusted by switching between a first switching frequency to a second switching frequency, and the first switching frequency and the second switching frequency are selected such that the first switching frequency and the second s