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EP-4184794-B1 - ANALOG-TO-DIGITAL CONVERTER AND METHOD FOR ANALOG-TO-DIGITAL CONVERSION

EP4184794B1EP 4184794 B1EP4184794 B1EP 4184794B1EP-4184794-B1

Inventors

  • FELDTKELLER, MARTIN

Dates

Publication Date
20260506
Application Date
20211123

Claims (11)

  1. An analog-to-digital converter (10) configured to output an n-bit signal in response to an analog input signal (anin), where n is greater than 1, comprising: n comparators (11), each comparator configured to output one bit of the n-bit signal and comprising a first input and a second input, wherein a first comparator (11_1) is configured to receive a reference value at its first input and the analog input signal at its second input and to output the first, most significant bit of the n bit signal, wherein for an i-th comparator (11_i), i= 2...n, configured to output an i-th bit, the analog-to-digital converter (10) comprises a respective i-th input device (12_i) configured to selectively provide one of 2 i-1 reference values to one of the first or second input of the i-th comparator (11_i) and the analog input signal (anin) to the other one of the first or second input of the i-th comparator (11_i) such that the n-bit signal is a Gray code representation of the analog input signal, wherein each i-th input device (12_i), i=2...n, is configured to be controlled by a logic combination of output signals of the first through (i-1)-th comparators (11), wherein the i-th input device is configured to switch the providing of the one of 2 i-1 reference values and the analog input signal (anin) between the first and second inputs of the i-th comparator (11_i) based on an XOR combination of the output signals of the first through (i-1)-th comparators (11).
  2. The analog-to-digital converter (10) of claim 1, wherein the input device (12_i) of the i-th comparator (11_i), i = 2...n, comprises a switch device (20; 31), which is configured to couple in a first position the first input of the i-th comparator (11_i) to a first reference set (21) and the second input of the i-th comparator (11_i) to the analog input signal (anin) and to couple in a second position the second input of the i-th comparator (11_i) to a second reference set (22) and the first input of the i-th comparator (11_i) to the analog input signal (anin).
  3. The analog-to-digital converter (10) of claim 2, wherein for the i-th comparator, i=2...n, the first reference set (21) is configured to provide one of first 2 i-2 reference values based on a logic combination of the outputs of the first through (i-2)-th comparators and wherein the second reference set (22) is configured to provide one of second 2 i-2 reference values different from the first 2 i-2 reference values based on the logic combination.
  4. The analog-to-digital converter (10) of any one of claims 1 to 3, wherein for providing one of 2 i-1 reference values the analog-to-digital converter (10) includes a digital-to-analog converter (61).
  5. The analog-to-digital converter (10) of any one of claims 1 to 4, wherein the analog-to-digital converter (10) is configured to operate independently from a clock signal.
  6. The analog-to-digital converter (10) of any one of claims 1 to 5, further comprising a peak detection logic coupled to receive the n-bit signal and to determine a peak value of the n-bit signal over time.
  7. The analog-to-digital converter (10) of claim 6, wherein the peak detection logic is configured to operate independently from a clock signal.
  8. The analog-to-digital converter (10) of claim 6 or 7, wherein the peak detection logic, for each i-th bit, i=1-n, comprises an i-th latch (80_i) configured to receive the 1-th bit, wherein the peak detection logic is configured such that of the n latches (80) at most one latch, the k-th latch (80_k), is switched to transparent providing its input to its output at a given time, wherein the k-th latch is selected from the first to n-th latch with decreasing priority as the latch where for the first to k-1 latches (80) the input corresponds to the output and for the k-th bit the decoded Gray code - indicates a higher value of the k-th bit than stored in the k-th latch when the peak detection logic is a maximum peak detection logic, or - indicates a lower value of the k-th bit than stored in the k-th latch when the peak detection logic is a minimum peak detection logic.
  9. An analog-to-digital conversion method for outputting an n-bit signal in response to an analog input signal (anin), where n is greater than 1, comprising: n comparators(11), each comparator (11) configured to output one bit of the n-bit signal and comprising a first input and a second input, providing a reference value to a first input of a first comparator and the analog input signal to a second input of the first comparator, and obtaining the 1 st , most significant bit of the n bit signal, at the output of the first comparator, and, for each i-th bit, i=2...n: selectively providing one of 2 i-1 reference values to one of the first or second input of a respective i-th comparator (11_i) and the analog input signal (anin) to the other one of the first or second input of the i-th comparator (11_i), and obtaining the i-th bit of the n bit signal at the output of the i-th comparator, such that the n-bit signal is a Gray code representation of the analog input signal (anin), wherein the selectively providing for the i-th bit is based on a logic combination of output signals of the first through (i-1)-th comparators (11), wherein for the i-th bit, the selectively providing comprises switching the providing of the one of 2 i-1 reference values and the analog input signal between the first and second inputs of the i-th comparator (11_i) based on an XOR combination of the output signals of the first through (i-1)-th comparators.
  10. The method of claim 9, further comprising compensating delays caused by the XOR combinations.
  11. The method of claim 9 or 10, further comprises detecting a peak in the n-bit signal over time.

Description

TECHNICAL FIELD The present application relates to analog-to-digital converters and to methods for analog-to-digital conversion. BACKGROUND Analog-to-digital converters generally relate to devices converting an analog input signal like a voltage signal or current signal into a digital signal. For example, in this way analog signals may be further processed digitally. One application of such analog-to-digital converters are integrated circuit devices that contain mainly analog functions, but in which for some functions a digital solution is desired. For example, analog solutions like sample and hold circuits, peak detectors or tendency detectors for detecting a rising or falling slope of a signal may use integrated capacitors. Integrated capacitors are difficult to implement because leakage currents in the circuit may discharge such capacitors faster than the signal changes. In such cases a digital solution may be implemented using for example a successive approximation register (SAR) or sigma-delta analog-to-digital converter, which require a clock signal and state machines to derive the desired digital signal from the output of the converter. Typically, clock generators for providing a corresponding clock signal require trimming, as the relevant components have high fabrication tolerances. Trimming causes extra logistic effort if the integrated circuit device itself does not need trimming of other parameters than the clock generator. For example, components like a bandgap reference may have sufficient accuracy without trimming, so if, apart from the clock generator, only such components not requiring trimming are present, the provision of the clock generator alone causes the trimming to be required. Therefore, for example, for low-cost solutions analog-to-digital converters operating without a clock signal are desirable. Generally, conventional analog-to-digital converter (ADC) not needing a clock signal include a resistor ladder to provide a plurality of reference voltage levels. Furthermore, a conventional ADC may include a comparator for each level to be determined, comparing an analog input signal to be converted with one of the reference values generated by the resistor ladder. The output of such a converter has a so-called thermometer code and may for example be used for bar graph displays where only a limited number of levels need to be determined, for example 16 different levels. Sick L. et al., "A dynamic reference A/D converter", IEEE Tencon 2003, Conference on Convergent Technologies for the Asia-Pacific Region, Vol. 3 XP010687425 discloses an analog-to-digital converter configured to output an n-bit signal in response to an analog input signal, where n is greater than 1, is provided, comprising: n comparators, each comparator configured to output one bit of the n-bit signal and comprising a first input and a second input,wherein a first comparator of n comparators is configured to receive the analog input signal at its first input and a reference value at its second input and to output the first, most significant bit of the n-bit signal,wherein for an i-th comparator, i= 2...n, configured to output an i-th bit, the analog-to-digital converter comprises a respective i-th input device configured to selectively provide one of 2i-1 reference values to one of the first orsecond input of the i-th comparator and the analog input signal to the other one of the first or second input of the i-th comparator. Each i-th input device, i=2...n, is configured to be controlled by a logic combination of output signals of the first through (i-1)-th comparators. Similar analog-to-digital converters are also disclosed in US 8 390 499 B2 or US 5 691 722 A. SUMMARY An analog-to-digital converter as defined in claim 1 and a method as defined in claim 9 are provided. The dependent claims define further embodiments. According to an embodiment, an analog-to-digital converter configured to output an n-bit signal in response to an analog input signal, where n is greater than 1, is provided, comprising: n comparators, each comparator configured to output one bit of the n-bit signal and comprising a first input and a second input,wherein a first comparator of n comparators is configured to receive the analog input signal at its first input and a reference value at its second input and to output the first, most significant bit of the n-bit signal,wherein for an i-th comparator, i= 2...n, configured to output an i-th bit, the analog-to-digital converter comprises a respective i-th input device configured to selectively provide one of 2i-1 reference values to one of the first or second input of the i-th comparator and the analog input signal to the other one of the first or second input of the i-th comparator such that the n-bit signal is a Gray code representation of the analog input signal. Each i-th input device, i=2...n, is configured to be controlled by a logic combination of output signals of the first through (i-1)-th co