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EP-4189512-B1 - HYBRID VOLTAGE REGULATOR WITH A WIDE REGULATED VOLTAGE RANGE

EP4189512B1EP 4189512 B1EP4189512 B1EP 4189512B1EP-4189512-B1

Inventors

  • HAFIZI, MADJID

Dates

Publication Date
20260506
Application Date
20210608

Claims (15)

  1. A chip, comprising: a voltage regulator (1310), wherein the voltage regulator comprises: a pass n-type field effect transistor, NFET, (1320) coupled between a first voltage rail (655) and a second voltage rail (660); a pass p-type field effect transistor, PFET, (1330) coupled between the first voltage rail and the second voltage rail; a first amplifier (1340) having an output (1346); a first switch (1322) coupled between the output of the first amplifier and a gate of the pass NFET; a second amplifier (1350) having an output (1356); a second switch (1324) coupled between the output of the second amplifier and a gate of the pass PFET; a third switch (1332) coupled between the gate of the pass NFET and a ground; a fourth switch (1334) coupled between the gate of the pass PFET and the second voltage rail; and a driver (610, 805, 905, 1005), wherein the driver comprises: a pull-down transistor (620) coupled between an output of the driver and the ground; a pull-up NFET (630) coupled between the first voltage rail and the output of the driver; a pull-up PFET (635) coupled between the first voltage rail and the output of the driver; a fifth switch (640) coupled between a gate of the pull-up NFET and the ground; and a sixth switch (642) coupled between a gate of the pull-up PFET and the second voltage rail (660); and wherein the driver is adapted to be operated in a N-over-N driver mode to support a first amplitude range, when the voltage (Vreg) on the first voltage rail (655) is within the first amplitude range, and operated in a P-over-N driver mode to support a second amplitude range, when the voltage (Vreg) on the first voltage rail (655) is within the second amplitude range.
  2. The chip of claim 1, further comprising a control circuit configured to: receive a control signal; turn on the first switch, turn off the second switch, turn off the third switch, and turn on the fourth switch if the control signal has one of a first set of values; and turn off the first switch, turn on the second switch, turn on the third switch, and turn off the fourth switch if the control signal has one of a second set of values.
  3. The chip of claim 1, further comprising: a serializer having an input and an output, wherein the output of the serializer is coupled to the driver; a circuit having an output coupled to the input of the serializer; and wherein the circuit comprises a processor.
  4. The chip of claim 1, further comprising a control circuit configured to: receive a control signal; turn on the first switch, turn off the second switch, turn off the third switch, turn on the fourth switch, turn off the fifth switch, and turn on the sixth switch if the control signal has one of a first set of values; and turn off the first switch, turn on the second switch, turn on the third switch, turn off the fourth switch, turn on the fifth switch, and turn off the sixth switch if the control signal has one of a second set of values.
  5. The chip of claim 1, further comprising: a fifth switch coupled between a first input of the first amplifier and the first voltage rail; and a sixth switch coupled between a first input of the second amplifier and the first voltage rail.
  6. The chip of claim 5, further comprising a reference circuit having a reference output coupled to a second input of the first amplifier and a second input of the second amplifier, wherein the reference circuit is configured to generate a reference voltage and output the reference voltage at the reference output.
  7. The chip of claim 6, wherein the reference circuit comprises: a current source coupled between the second voltage rail and the reference output; and a variable resistor coupled between the reference output and a ground, wherein the variable resistor is configured to receive a control signal and set a resistance of the variable resistor based on the control signal.
  8. The chip of claim 6, wherein the reference circuit comprises: a reference resistor coupled between the second voltage rail and the reference output; and a variable resistor coupled between the reference output and a ground, wherein the variable resistor is configured to receive a control signal and set a resistance of the variable resistor based on the control signal.
  9. The chip of claim 6, wherein the reference circuit is configured to: receive a control signal; set a voltage level of the reference voltage based on the control signal; and further comprising a control circuit configured to: receive the control signal; turn on the first switch, turn off the second switch, turn off the third switch, turn on the fourth switch, turn on the fifth switch, and turn off the sixth switch if the control signal has one of a first set of values; and turn off the first switch, turn on the second switch, turn on the third switch, turn off the fourth switch, turn off the fifth switch, and turn on the sixth switch if the control signal has one of a second set of values.
  10. The chip of claim 1, further comprising: a first compensation circuit coupled to the gate of the pass NFET; a second compensation circuit coupled to the gate of the pass PFET; and a fifth switch coupled between the second compensation circuit and a drain of the PFET.
  11. The chip of claim 10, wherein the first compensation circuit comprises a first compensation capacitor and the second compensation circuit comprises a second compensation capacitor.
  12. The chip of claim 10, further comprising a control circuit configured to: receive a control signal; turn on the first switch, turn off the second switch, turn off the third switch, turn on the fourth switch, and turn off the fifth switch if the control signal has one of a first set of values; and turn off the first switch, turn on the second switch, turn on the third switch, turn off the fourth switch, and turn on the fifth switch if the control signal has one of a second set of values.
  13. A method (2000) of operating a hybrid voltage regulator of a chip, wherein the voltage regulator comprises a pass n-type field effect transistor, NFET, coupled between a first voltage rail and a second voltage rail, and a pass p-type field effect transistor, PFET, coupled between the first voltage rail and the second voltage rail, the chip further comprising a driver, wherein the driver comprises a pull-down transistor coupled between an output of the driver and the ground, a pull-up NFET coupled between the first voltage rail and the output of the driver, a pull-up PFET coupled between the first voltage rail and the output of the driver, a fifth switch coupled between a gate of the pull-up NFET and the ground, a sixth switch coupled between a gate of the pull-up PFET and the second voltage rail, the method comprising: in a first regulation mode, turning (2010) off the pass PFET; in the first regulation mode, driving (2020) a gate of the pass NFET based on a reference voltage and a feedback voltage, wherein the feedback voltage provides feedback of a voltage on the first voltage rail; in a second regulation mode, turning (2030) off the pass NFET; and in the second regulation mode, driving (2040) a gate of the pass PFET based on the reference voltage and the feedback voltage; and wherein the driver is operated in a N-over-N driver mode to support a first amplitude range and is operated in a P-over-N driver mode to support a second amplitude range, and wherein the first regulation mode coincides with the N-over-N driver mode and the second regulation mode coincides with the P-over-N driver mode.
  14. The method of claim 13, wherein the feedback voltage is proportional to the voltage on the first voltage rail; and wherein: driving the gate of the pass NFET based on the reference voltage and the feedback voltage comprises driving the pass NFET in a direction that reduces a difference between the reference voltage and the feedback voltage; and driving the gate of the pass PFET based on the reference voltage and the feedback voltage comprises driving the pass PFET in a direction that reduces a difference between the reference voltage and the feedback voltage.
  15. The method of claim 13, further comprising: receiving a control signal; setting a voltage level of the reference voltage based on the control signal; and further comprising: operating the voltage regulator in the first regulation mode if the control signal has one of a first set of values; and operating the voltage regulator in the second regulation mode if the control signal has one of a second set of values.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS The present application claims priority to and the benefit of Non-Provisional Application Serial No. 16/941,230 filed in the United States Patent and Trademark Office on July 28, 2020 and Non-Provisional Application Serial No. 16/941,261 filed in the United States Patent and Trademark Office on July 28, 2020. Field Aspects of the present disclosure relate generally to voltage regulators, and more particularly, to a hybrid voltage regulator with a wide regulated voltage range. Background Voltage regulators are used in a variety of systems to provide regulated voltages to power circuits in the systems. A commonly used voltage regulator is a low dropout (LDO) regulator. An LDO regulator may be used to provide a clean regulated voltage to power a circuit (e.g., a driver). An LDO regulator typically includes a pass transistor and an error amplifier in which the output of the error amplifier drives the gate of the pass transistor based on a reference voltage and feedback of the regulated voltage. Attention is further drawn to US 7 723 969 B1 describing a system and a method for providing a low drop out circuit that can efficiently and correctly handle a wide range of input voltages. A power supply control circuit is provided for a low drop out circuit that comprises an operational amplifier that is coupled to a low drop out transistor. A switcher circuit provides one of a plurality of operating voltages to the low drop out transistor. The power supply control circuit provides a value of an operating voltage to the operational amplifier that enables the operational amplifier to operate the low drop out transistor in a manner that prevents the low drop out transistor from being out of control. Attention is drawn to US 9 240 784 B2 describing a single-ended configurable multimode driver. An example of an apparatus includes an input to receive an input signal, an output to transmit a driven signal generated from the input signal on a communication channel, a mechanism for independently configuring a termination resistance of the driver apparatus, and a mechanism for independently configuring a voltage swing of the driven signal without modifying a supply voltage for the apparatus. SUMMARY The present invention is set forth in the independent claims. Preferred embodiments of the invention are described in the dependent claims. The following presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an extensive overview of all contemplated implementations and is intended to neither identify key or critical elements of all implementations nor delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description that is presented later. A first aspect relates to a chip including a voltage regulator. The voltage regulator includes a pass n-type field effect transistor (NFET) coupled between a first voltage rail and a second voltage rail, and a pass p-type field effect transistor (PFET) coupled between the first voltage rail and the second voltage rail. The voltage regulator also includes a first amplifier having an output, a first switch coupled between the output of the first amplifier and a gate of the pass NFET, a second amplifier having an output, and a second switch coupled between the output of the second amplifier and a gate of the pass PFET, a third switch coupled between the gate of the pass NFET and a ground, and a fourth switch coupled between the gate of the pass PFET and the second voltage rail. A second aspect relates to a method of operating a hybrid voltage regulator. The voltage regulator includes a pass n-type field effect transistor (NFET) coupled between a first voltage rail and a second voltage rail, and a pass p-type field effect transistor (PFET) coupled between the first voltage rail and the second voltage rail. The method includes, in a first regulation mode, turning off the pass PFET, and driving a gate of the pass NFET based on a reference voltage and a feedback voltage, wherein the feedback voltage provides feedback of a voltage on the first voltage rail. The method also includes, in a second regulation mode, turning off the pass NFET, and driving a gate of the pass PFET based on the reference voltage and the feedback voltage. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows an example of a system including a first chip, a second chip, and drivers for chip-to-chip communication according to certain aspects of the present disclosure.FIG. 2 shows an example of a system in which Serializer/Deserializer (SerDes) is used for chip-to-chip communication according to certain aspects of the present disclosure.FIG. 3 shows an example of a system in which differential links are used for chip-to-chip communication according to certain aspects of the present d