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EP-4191307-B1 - SEMICONDUCTOR ASSEMBLY WITH WAVEGUIDE AND GLASS SUBSTRATE

EP4191307B1EP 4191307 B1EP4191307 B1EP 4191307B1EP-4191307-B1

Inventors

  • NIE, BAI
  • DUONG, BENJAMIN
  • TADAYON, POOYA
  • ARANA, LEONEL R.
  • LI, YONGGANG
  • LIU, CHANGHUA
  • DARMAWIKARTA, KRISTOF
  • Pietambaram, Srinivas Venkata Ramanuja
  • IBRAHIM, Tarek A.
  • MAHALINGAM, HARI

Dates

Publication Date
20260513
Application Date
20220909

Claims (11)

  1. A semiconductor assembly (200) comprising: a lower first glass substrate (110); an upper electronic integrated circuit, EIC, (120) attached to the first glass substrate (110); an upper photonic integrated circuit, PIC (130) configured to produce and/or receive an optical frequency, the PIC being attached to the first glass substrate (110) and comprising an optical port (132); a bridge die (150) electrically connecting the PIC (130) and the EIC (120), wherein the bridge die(150) is attached to the first glass substrate (110); and a coupling adapter (114) for connecting the PIC (130) to an optical fiber,the coupling adapter (114) being bonded to the first glass substrate (110) and comprising: a coupling port (144) configured for connecting the PIC (130) to an optical fiber; and a waveguide (240) formed in the coupling adapter (140) and extending between the coupling port (144) and the optical port (132) of the PIC (130), wherein the waveguide (240) is curved upwardly so that it exits to the coupling port at a top surface of the assembly (200).
  2. The assembly (200) of claim 1, further comprising a second glass substrate (112), wherein the first glass substrate (110) and the second glass substrate (112) are bound to each other by one or more glass-to-glass bonds.
  3. The assembly (200) of claim 1, further comprising an optical fiber connecting to the coupling port (144).
  4. The assembly (200) of claim 1, wherein the coupling port (144) comprises V-grooves.
  5. The assembly (200) of claim 1, wherein the coupling adapter (114) comprises a glass adapter.
  6. The assembly (200) of claim 1, wherein the bridge die (150) is silicon bridge die.
  7. The assembly (200) of claim 1, wherein the EIC (120) and the PIC (130) are coupled to each other through the bridge die (150) and one or more through one or more power delivery pathways.
  8. The assembly (200) of claim 1, further comprising a second glass substrate (112).
  9. The assembly (200) of claim 1, wherein the waveguide (240) comprises a laser-modified pathway.
  10. A method of making a semiconductor assembly (200), the method comprising: attaching a bridge (150) die to a lower first glass substrate (110); attaching an upper electronic integrated circuit , EIC, (120) to the first glass substrate (110) and the bridge die (150); attaching an upper photonic integrated circuit, PIC, (130) to the first glass substrate (110) and the bridge die (150), wherein the EIC (120) is electrically coupled to the PIC (130) through the bridge die (150) and wherein the PIC (130) is configured to produce and/or receive an optical frequency and comprises an optical port (132); bonding a coupling adapter (114) to the first glass substrate (110), the coupling adapter (114) comprising a coupling port (144) for connecting the PIC (130) to an optical fiber; and forming a waveguide (240) in the coupling adapter (114), the waveguide (240) aligning with the PIC (130) and extending between the coupling port (144) and the optical port (132) of the PIC (130), the waveguide (240) being curved upwardly so that it exits to the coupling port (144) at a top surface of the assembly (200), wherein forming the waveguide (240) comprises a laser direct writing.
  11. The method of claim 10, further comprising attaching a second glass substrate (112) to the first glass substrate (110) prior to attaching the bridge die (150), wherein attaching the second glass substrate (112) comprises using glass to glass bonding with a laser.

Description

TECHNICAL FIELD The invention relates to a semiconductor assembly and a method of making a semiconductor assembly. BACKGROUND Silicon photonics are a good candidate for low cost and high performance components, such as for increasing data centric technology. But packaging silicon photonics can be challenging, and result in compatibility and integration challenges due to mode field diameter mismatch and tight alignment tolerance. It is desired to have a low cost and efficient packaging technology that address these concerns, and other technical challenges. Documents US 2021/041649 A1 and EP 3 872 547 A1 reflect the state of the art. Document EP 4 155 788 A1 is relevant within the terms of Article 54(3) EPC. BRIEF DESCRIPTION OF THE DRAWINGS In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. Like numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various assemblies discussed in the present document. FIG. 1 illustrates a semiconductor assembly in an example not encompassed by the wording of the claims but which is considered useful for understanding the invention.FIG. 2 illustrates a semiconductor assembly in an example.FIG. 3 a flow diagram of a method of making a semiconductor assembly in an example not encompassed by the wording of the claims but which is considered useful for understanding the invention.FIG. 4 illustrates a system level diagram. DETAILED DESCRIPTION A semiconductor assembly in accordance with the invention is defined in claim 1. A method of making a semiconductor assembly in accordance with the invention is defined in claim 10. Note that the examples and/or embodiments discussed hereinbelow in relation to any of the figures 1, 3A-I and 4 are not encompassed by the wording of the claims but are considered useful for understanding the invention. Disclosed herein is a semiconductor assembly and method of making the same for Silicon Photonics (SiP) packaging with a waveguide. Here, laser based technology is used to integrate a photonic integrated circuit (PIC), an electronic integrated circuit (EIC) and a substrate, with low-loss coupling between an optical fiber and SiP packaging. Laser made glass-to-glass bonds are used, and an embedded waveguide is made through laser direct writing (LDW). Silicon photonics (SiP) is a combination of silicon integrated circuits and semiconductor lasers, from which photonic integrated circuits (PICs) can be made. PICs can produce or detect optical light with single or multiple frequencies. PICs can extend, enable, and increased data transmission, while consuming less power than conventional circuits. Such PICs can allow for energy efficient bandwidth scaling. PICs can allow for faster data transmission over longer distances compared to traditional electronics. However, silicon photonics packaging can be challenging. Fiber coupling compatibility and integration with electronic integrated circuits (EIC) can be difficult due to mode field diameter mismatches and tight alignment tolerances. The use of waveguides in glass can be a good solution for such SiP packaging, due in part to the optical and mechanical properties of glass. Discussed herein, laser based technology can be leveraged to integrate PICs, EICs, and substrates. Laser based technology can also enable in situ waveguide formation in glass substrates to create low-loss coupling between SiP packages and coupling fibers. In situ formation of the waveguide can minimize the coupling loss between PIC and the package. Both low temperature glass-to-glass bonding by laser and embedded waveguide in glass by laser direct writing can be used. The discussed methods and devices can allow for creation of low loss and high voltage compatible SiP packaging. FIG. 1 illustrates a semiconductor assembly 100 in an example. The semiconductor assembly 100 can include a first glass substrate 110, a second glass substrate 112, a glass adapter 114, a first integrated circuit 120, a second integrated circuit 130 with an optical port 132, a waveguide 140, a fiber port 144, a bridge die 150 with connections 152, and a substrate 160. In the assembly 100, the substrate 160 can host the glass substrates 110 and112. The bridge die 150 can be situated in the glass substrate 112, connecting the first integrated circuit 120 and the second integrated circuit 130. The waveguide 140 can be situated within a glass adapter 114, and aligned with an optical port 132 of the second integrated circuit 130. The glass substrates 110, 112, and adapter 114, can be, for example, a silicon dioxide or borosilicate glass. In some cases, alternative glass materials can be used. Shown in FIG. 1, the glass substrates 110, 112 are two stacked and bonded glass substrates, while the glass adapter 114 is a separate piece hosting the waveguide 140 and fiber cou