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EP-4200909-B1 - MEMORY PERIPHERAL CIRCUIT HAVING THREE-DIMENSIONAL TRANSISTORS AND METHOD FOR FORMING THE SAME

EP4200909B1EP 4200909 B1EP4200909 B1EP 4200909B1EP-4200909-B1

Inventors

  • SUN, CHAO
  • CHEN, LIANG
  • XU, WENSHAN
  • LIU, WEI
  • JIANG, NING
  • XUE, LEI
  • TIAN, Wu

Dates

Publication Date
20260506
Application Date
20210630

Claims (13)

  1. A three-dimensional, 3D, memory device (100), comprising: a first semiconductor structure (102) comprising an array (201) of memory cells (206); a second semiconductor structure (104) comprising a peripheral circuit (202), wherein the peripheral circuit (202) comprises a 3D transistor (500), wherein the respective 3D transistors (500) comprise a 3D semiconductor body (505) and a gate structure (508) in contact with a plurality of sides of the 3D semiconductor body (505), the gate structure (508) comprising a gate dielectric (602) and a gate electrode (604), wherein the peripheral circuit (202) comprises a first peripheral circuit (902) being a LLV peripheral circuit provided with a first voltage between 0.9 V and 2.0 V and a second peripheral circuit (904) being a LV peripheral circuit provided with a second voltage between 2.0 V and 3.3 V, wherein the 3D transistors comprise a first 3D transistor (1100) of the first peripheral circuit (902) and a second 3D transistor (2000) of the second peripheral circuit (904); and a bonding interface (106) between the first semiconductor structure (102) and the second semiconductor structure (104), wherein the array of memory cells is coupled to the peripheral circuit across the bonding interface (106), wherein the peripheral circuit further comprises a third peripheral circuit (906) being a HV peripheral circuit provided with a third voltage greater than 3.3 V, the 3D transistors further comprise a third 3D transistor (2100) of the third peripheral circuit (906), wherein the first semiconductor structure (102) further comprises a plurality of bit lines (216) and a plurality of word lines (218) coupled to the array of memory cells (201); the second 3D transistor (2000) of the second peripheral circuit (904) is coupled to the array of memory cells (201) through at least one of the bit lines (216); and the third 3D transistor (2100) of the third peripheral circuit (906) is coupled to the array of memory cells (201) through at least one of the word lines (218) and wherein the thickness of the gate dielectric (1107) of the first 3D transistor (1100) is between 2 nm and 4 nm, the thickness of the gate dielectric (2007) of the second 3D transistor (2000) is between 5 nm and 8 nm, and the thickness of the gate dielectric (2107) of the third 3D transistor (2100) is greater than 10 nm, and wherein the third 3D transistor further comprises a drift region, and a source and a drain, and a doping concentration of the drift region is smaller than a doping concentration of the source and drain.
  2. The 3D memory device (100) of claim 1, wherein the 3D transistor is a multi-gate transistor.
  3. The 3D memory device (100) of claim 1, wherein the first 3D transistor of the first peripheral circuit receives the first voltage, and the second 3D transistor of the second peripheral circuit receives the second voltage greater than the first voltage.
  4. The 3D memory device (100) of claim 1, wherein the third 3D transistor of the third peripheral circuit receives the third voltage greater than the second voltage, wherein the first peripheral circuit comprises preferably an input/output (I/O) circuit, the second peripheral circuit comprises at least part of a page buffer, and the third peripheral circuit comprises a word line driver.
  5. The 3D memory device (100) of any one of claims 1-4, - wherein the gate electrode of the first 3D transistor comprises a metal, and the gate dielectric of the first 3D transistor comprises a high-dielectric constant (high-k) dielectric; and/or - wherein the 3D semiconductor body (505) of the first 3D transistor or the second 3D transistor has a dumbbell shape in a plan view.
  6. The 3D memory device (100) of any one of claims 1-5, wherein - a width of the 3D semiconductor body (505) is greater than 10 nm, wherein preferably the width of the 3D semiconductor body (505) is between 30 nm and 1,000 nm; and/or - a height of the 3D semiconductor body (505) is greater than 40 nm, wherein preferably the height of the 3D semiconductor body (505) is between 50 nm and 1,000 nm; and/or - a channel length of the 3D semiconductor body (505) is greater than 30 nm, wherein preferably the channel length of the 3D semiconductor body (505) is between 50 nm and 1,500 nm.
  7. The 3D memory device (100) of any one of claims 1 - 6, wherein a thickness of the gate dielectric (1107, 2007, 2107) is greater than 1.8 nm, preferably wherein the thickness of the gate dielectric is between 2 nm and 100 nm.
  8. The 3D memory device (100) of any one of claims 1-7, wherein the peripheral circuit further comprises a planar transistor.
  9. The 3D memory device (100) of claim 8, wherein the peripheral circuit further comprises: another 3D transistor; another planar transistor; a first trench isolation between the 3D transistor and the another 3D transistor; and a second trench isolation between the planar transistor and the another planar transistor.
  10. The 3D memory device (100) of claim 9, wherein the first trench isolation and the second trench isolation have different depths, wherein preferably the second trench isolation has a greater depth than the first trench isolation.
  11. A system, comprising: a memory device (100) configured to store data according to claim 1; and a memory controller coupled to the memory device and configured to control the array of memory cells through the peripheral circuit.
  12. A method for forming a three-dimensional , 3D, memory device (100), comprising: forming, on a first substrate, a first semiconductor structure (102) comprising an array of memory cells (201); forming, on a second substrate, a second semiconductor structure (104) comprising a peripheral circuit (202), wherein the peripheral circuit (202) comprises 3D transistors (500); and bonding the first semiconductor structure (102) and the second semiconductor structure (104) in a face-to-face manner, such that the array of memory cells (201) is coupled to the peripheral circuit (202) across a bonding interface (106), wherein the 3D transistors (500) comprise a respective 3D semiconductor body (505) and a gate structure (508) in contact with a plurality of sides of the 3D semiconductor body (505), the gate structure (508) comprising a gate dielectric (602) and a gate electrode (604), wherein the peripheral circuit (202) comprises a first peripheral circuit (902) being a LLV peripheral circuit provided with a voltage between 0.9 V and 2.0 V and a second peripheral circuit (904) being a LV peripheral circuit provided with a voltage between 2.0 V and 3.3 V, wherein the 3D transistors (500) comprise a first 3D transistor (1100) of the first peripheral circuit (902) and a second 3D transistor (2000) of the second peripheral circuit (904), wherein the peripheral circuit (202) further comprises a third peripheral circuit (906) being a HV peripheral circuit provided with a voltage greater than 3.3 V, the 3D transistors (500) further comprise a third 3D transistor (2100) of the third peripheral circuit (906), wherein the first semiconductor structure (102) further comprises a plurality of bit lines (216) and a plurality of word lines (218) coupled to the array of memory cells (201); the second 3D transistor (2000) of the second peripheral circuit (904) is coupled to the array of memory cells (201) through at least one of the bit lines (216); and the third 3D transistor (2100) of the third peripheral circuit (906) is coupled to the array of memory cells (201) through at least one of the word lines (218) and wherein the thickness of the gate dielectric (1107) of the first 3D transistor (1100) is between 2 nm and 4 nm, the thickness of the gate dielectric (2007) of the second 3D transistor (2000) is between 5 nm and 8 nm, and the thickness of the gate dielectric (2107) of the third 3D transistor (2100) is greater than 10 nm, and wherein the third 3D transistor further comprises a drift region, and a source and a drain, and a doping concentration of the drift region is smaller than a doping concentration of the source and drain.
  13. The method of claim 12, wherein forming the second semiconductor structure (104) comprises: forming a 3D semiconductor body (505) from the second substrate; and forming a gate structure (408) in contact with a plurality of sides of the 3D semiconductor body (505), wherein preferably forming the 3D semiconductor body (505) comprises: forming a trench isolation (404) in the second substrate surrounding a portion of the second substrate; and etching back the trench isolation (404) to expose at least part of the portion of the second substrate.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS BACKGROUND The present disclosure relates to memory devices and fabrication methods thereof. Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As a result, memory density for planar memory cells approaches an upper limit. A three-dimensional (3D) memory architecture can address the density limitation in planar memory cells. The 3D memory architecture includes a memory array and peripheral circuits for facilitating operations of the memory array. Document US2020/0328186A1 discloses a 3D SC device with a microprocessor chip which includes at least one microprocessor device on a first substrate and a first interconnect layer disposed on the at least one microprocessor device, the first interconnect layer including at least one first interconnect structure and with a first memory chip, having at least one first memory cell on a second substrate and a second interconnect layer disposed on the at least one first memory cell, the second interconnect layer including at least one second interconnect structure and with a second memory chip, having at least one second memory cell on a third substrate and a third interconnect layer disposed on the at least one second memory cell, the third interconnect layer including at least one third interconnect structure, wherein the first interconnect layer of the microprocessor chip is bonded with the second substrate of the first memory chip, and the at least one microprocessor device of the microprocessor chip is electrically connected with the at least one first memory cell of the first memory chip through the at least one first interconnect structure or the at least one second interconnect structure. Document US 2021/066281 A1 mentions the use of finFETs as peripheral transistors (figure 7A-7D and paragraph [0057]). SUMMARY The invention provides a three dimensional memory device according to claim 1 and a method of forming a three dimensional memory device according to claim 12. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate aspects of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure. FIG. 1A illustrates a schematic view of a cross-section of a 3D memory device, according to some aspects of the present disclosure.FIG. 1B illustrates a schematic view of a cross-section of another 3D memory device, according to some aspects of the present disclosure.FIG. 2 illustrates a schematic circuit diagram of a memory device including peripheral circuits, according to some aspects of the present disclosure.FIG. 3 illustrates a block diagram of a memory device including a memory cell array and peripheral circuits, according to some aspects of the present disclosure.FIG. 4 illustrates a perspective view of a planar transistor, according to some aspects of the present disclosure.FIG. 5 illustrates a perspective view of a 3D transistor, according to some aspects of the present disclosure.FIGs. 6A and 6B illustrate side views of two cross-sections of the 3D transistor in FIG. 5, according to some aspects of the present disclosure.FIGs. 7A-7I illustrate side views of cross-sections of various 3D transistors, according to various aspects of the present disclosure.FIG. 8A illustrates a side view of a cross-section of a 3D memory device, according to some aspects of the present disclosure.FIG. 8B illustrates a side view of a cross-section of another 3D memory device, according to some aspects of the present disclosure.FIG. 8C illustrates a side view of a cross-section of still another 3D memory device, according to some aspects of the present disclosure.FIG. 9 illustrates a block diagram of peripheral circuits provided with various voltages, according to some aspects of the present disclosure.FIG. 10 illustrates a block diagram of a memory device including an input/output (I/O) circuit, according to some aspects of the present disclosure.FIGs. 11A and 11B illustrate a perspective view and a side view, respectively, of a 3D transistor in the I/O circuit of FIG. 10, according to some aspects of the present disclosure.FIGs. 12A and 12B illustrate a perspective view and a side view, respectively, of a planar transistor.FIG. 13 illustrates a block diagram of a memory device including a word line driver and a page buffer, according to some aspects of the present disclosure.FIG. 14 illustrates schematic circuit diagrams of the word line driver and the page buffer in FIG. 13, according to some aspects of the present disclosure.FIG. 15 illustrates a schematic plan view of a me