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EP-4205168-B1 - INTEGRATED CIRCUIT (IC) PACKAGE SUBSTRATE WITH EMBEDDED TRACE SUBSTRATE (ETS) LAYER ON A SUBSTRATE, AND RELATED FABRICATION METHODS

EP4205168B1EP 4205168 B1EP4205168 B1EP 4205168B1EP-4205168-B1

Inventors

  • KANG, Kuiwon
  • KIM, CHIN-KWAN
  • PARK, JOONSUK

Dates

Publication Date
20260506
Application Date
20210819

Claims (15)

  1. A package substrate (204, 300) for an integrated circuit, IC, package, comprising: a substrate, comprising: an upper substrate metallization layer (238) comprising one or more substrate metal interconnects (240, 340); and an embedded trace substrate, ETS, layer coupled to the substrate, the ETS layer (206, 306) comprising: an ETS interconnect layer (242, 342) adjacent to the upper substrate metallization layer (238) of the substrate, the ETS interconnect layer (242, 342) comprising one or more ETS interconnects (246, 346); each ETS interconnect (246, 346) among the one or more ETS interconnects (246, 346) coupled to a substrate metal interconnect (240, 340) among the one or more substrate metal interconnects (240, 340) in the upper substrate metallization layer (238) of the substrate; characterized in that it comprises one or more metal pillar interconnects (208, 308) each coupling an ETS interconnect (246, 346) among the one or more ETS interconnects (246, 346), to a substrate metal interconnect (240, 340) among the one or more substrate metal interconnects (240, 340), wherein the ETS interconnect layer (242, 342) comprises an ETS interconnect layer outer surface (212, 244, 344); wherein the one or more ETS interconnects (246, 346) are adjacent to the ETS interconnect layer outer surface (212, 244, 344); wherein the one or more metal pillar interconnects (208, 308) each comprises a first surface extending a distance from the ETS interconnect layer outer surface (212, 244, 344).
  2. The package substrate (204, 300) of claim 1, wherein the substrate comprises a cored substrate (226), or wherein the substrate comprises a coreless substrate (326).
  3. The package substrate (204, 300) of claim 1, wherein a line-spacing ratio, L/S, of each ETS interconnect (246, 346) among the one or more ETS interconnects (246, 346) is less than 5.0/5.0.
  4. The package substrate (204, 300) of claim 1, wherein the distance of a portion of the one or more metal pillar interconnects (208, 308) extending from the ETS interconnect layer outer surface (212, 244, 344) is equal to or greater than five, 5, micrometers, µm, or wherein each of the one or more metal pillar interconnects (208, 308) extends through the one or more ETS interconnects (246, 346) and is coupled to the substrate metal interconnect (240, 340) among the one or more substrate metal interconnects (240, 340) in the upper substrate metallization layer (238) of the substrate.
  5. The package substrate (204, 300) of claim 1, wherein each of the one or more metal pillar interconnects (208, 308) comprises a second surface coupled to the substrate metal interconnect (240, 340) among the one or more substrate metal interconnects (240, 340) in the upper substrate metallization layer (238) of the substrate.
  6. The package substrate (204, 300) of claim 5, wherein each of the one or more metal pillar interconnects (208, 308) has a thickness of a second distance equal to or greater than ten (10) micrometers (µm) between the first surface of each of the one or more metal pillar interconnects (208, 308) and the second surface of each of the one or more metal pillar interconnects (208, 308).
  7. The package substrate (204, 300) of claim 1, wherein a ratio of a thickness of the one or more metal pillar interconnects (208, 308) to a thickness of the ETS interconnect layer (242, 342) is at least 1.4, or wherein a line-spacing ratio (L/S) of the one or more metal pillar interconnects (208, 308) is less than 5.0/5.0, or further comprising a solder resist layer (252, 352) comprising a second surface and a third surface coupled to the ETS layer (206, 306), at least one of the one or more metal pillar interconnects (208, 308) further extending through the solder resist layer (252, 352) and further extending a second distance above the second surface of the solder resist layer (252, 352).
  8. The package substrate (204, 300) of claim 1, wherein: the substrate further comprises at least one additional substrate metallization layer adjacent to the upper substrate metallization layer (238), wherein the upper substrate metallization layer (238) is disposed between the ETS layer (206, 306) and the at least one additional substrate metallization layer; and each of the at least one additional substrate metallization layer comprises one or more additional substrate metal interconnects (240, 340); and at least one of the one or more additional substrate metal interconnects (240, 340) are coupled to at least one of the one or more substrate metal interconnects (240, 340) in the upper substrate metallization layer (238).
  9. An integrated circuit, IC, package, comprising: a package substrate (204, 300) of any of the previous claims; and a die (210) coupled to the first surface of the one or more metal pillar interconnects (208, 308) to couple to at least one ETS interconnect (246, 346) among the one or more ETS interconnects (246, 346) in the ETS layer (206, 306).
  10. The IC package (202, 802, 903) of claim 9, wherein: the one or more ETS interconnects (246, 346) comprise a plurality of ETS interconnects (246, 346); a plurality of die interconnects (214, 216) coupled to the die (210); and each die (210) interconnect among the plurality of die interconnects (214, 216) is coupled to an ETS interconnect (246, 346) among the plurality of ETS interconnects (246, 346).
  11. The IC package of claim 10, wherein each of the one or more metal pillar interconnects (208, 308) comprises a second surface (248) coupled to the substrate metal interconnect among the one or more substrate metal interconnects in the upper substrate metallization layer (238) of the substrate (226).
  12. The IC package (202, 802, 903) of claim 10, wherein: the upper substrate metallization layer (238) further comprises one or more second substrate metal interconnects (240, 340); and the ETS interconnect layer (242, 342) comprises one or more second ETS interconnects (246, 346); each second ETS interconnect among the one or more second ETS interconnects (246, 346) coupled to a second substrate metal interconnect among the one or more second substrate metal interconnects (240, 340) in the upper substrate metallization layer (238) of the substrate; and further comprising: a second die; a plurality of second die interconnects coupled to the second die; each second die interconnect among the plurality of second die interconnects coupled to a second ETS interconnect among the one or more second ETS interconnects (246, 346); and at least one ETS interconnect (246, 346) among the one or more ETS interconnects (246, 346) that is coupled to at least one die (210) interconnect among the plurality of die interconnects (214, 216), is coupled to at least one second ETS interconnect among the one or more second ETS interconnects (246, 346) that is coupled to at least one second die interconnect among the plurality of second die interconnects.
  13. A method (400) of fabricating a substrate for an integrated circuit, IC, package (102, 202), comprising: forming (402) a substrate comprising an upper substrate metallization layer (238) comprising one or more substrate metal interconnects (240, 340); and forming (404) an embedded trace substrate, ETS, layer (206, 306) coupled to the substrate, the ETS layer (206, 306) comprising an ETS interconnect layer (242, 342) adjacent to the upper substrate metallization layer (238) of the substrate, the ETS interconnect layer (242, 342) comprising one or more ETS interconnects (246, 346); and disposing (406) the ETS layer (206, 306) on the substrate adjacent to the upper substrate metallization layer (238) coupling each ETS interconnect (246, 346) among the one or more ETS interconnects (246, 346) coupled to a substrate metal interconnect (240, 340) among the one or more substrate metal interconnects (240, 340) in the upper substrate metallization layer (238) of the substrate, further comprising forming one or more metal pillar interconnects (208, 308) coupled to an ETS interconnect (246, 346) among the one or more ETS interconnects (246, 346) and coupled to a substrate metal interconnect (240, 340) among the one or more substrate metal interconnects (240, 340), wherein forming the one or more metal pillar interconnects (208, 308) further comprises forming the one or more metal pillar interconnects (208, 308) for a first surface of the one or more metal pillar interconnects (208, 308) to extend a distance from an ETS interconnect layer outer surface (212, 244, 344) of the ETS interconnect layer (242, 342).
  14. The method (400) of claim 13, further comprising: forming a dielectric laminate (504); and laminate bonding the ETS layer (206, 306) to the substrate using the dielectric laminate (504).
  15. The method (400) of claim 13, wherein forming the one or more metal pillar interconnects comprises: forming one or more first openings through the ETS interconnect down to an outer surface of the one or more substrate metal interconnects; forming a first and second post on each respective side of the one or more first openings to form one or more second openings above the respective one or more first openings, the first and second post each disposed a second distance above the ETS interconnect layer outer surface; and disposing a metal material in the one or more second openings and the one or more first opening to form the one or more metal pillar interconnects in the respective one or more first openings and the one or more second openings, wherein forming the one or more first openings preferably comprises laser etching the one or more first openings through the ETS interconnect (246, 346) down to a top surface (702) of the one or more substrate metal interconnects (240, 340).

Description

PRIORITY APPLICATIONS The present application claims priority to U.S. Provisional Patent Application Serial No. 63/070,048, filed August 25, 2020 and entitled "INTEGRATED CIRCUIT (IC) PACKAGES EMPLOYING CORELESS SUBSTRATE WITH RAISED METAL PILLAR INTERCONNECTS FOR PROVIDING INTERCONNECTIONS TO AN IC DIE, AND RELATED FABRICATION METHODS,". The present application also claims priority to U.S. Patent Application Serial No. 17/405,494, filed August 18, 2021 and entitled "INTEGRATED CIRCUIT (IC) PACKAGE SUBSTRATE WITH EMBEDDED TRACE SUBSTRATE (ETS) LAYER ON A SUBSTRATE, AND RELATED FABRICATION METHODS,". BACKGROUND I. Field of the Disclosure The field of the disclosure relates to integrated circuit (IC) packages that include one or more semiconductor dies attached to a package substrate that provides an electrical interface to the semiconductor dice to provide a die-to-die interconnection. II. Background Integrated circuits (ICs) are the cornerstone of electronic devices. ICs are packaged in an IC package, also called a "semiconductor package" or "chip package." The IC package includes one or more semiconductor dies, also referred to "IC dies" or "dies." The dies are mounted on and electrically coupled to a package substrate to provide physical support and an electrical interface to the semiconductor die(s). The package substrate may be a coreless embedded trace substrate (ETS), for example, that includes embedded electrical traces in one or more dielectric layers and vertical interconnect accesses (vias) coupling the electrical traces together to provide electrical interfaces between the semiconductor die(s). The semiconductor die(s) is mounted to and electrically interfaced to interconnects exposed in a top or outer layer of the package substrate to electrically couple the semiconductor die(s) to the electrical traces of the package substrate. The semiconductor die(s) and package substrate are encapsulated in a package material, such as a molding compound, to form the IC package. The IC package may also include external solder balls in a ball grid array (BGA) that are electrically coupled to interconnects exposed in a bottom layer of the package substrate to electrically couple the solder balls to the electrical traces in the package substrate. The solder balls provide an external electrical interface to the semiconductor die(s) in the IC package. The solder balls are electrically coupled to metal contacts on a printed circuit board (PCB) when the IC package is mounted to the PCB to provide an electrical interface between electrical traces in the PCB to the IC chip through the package substrate in the IC package. US 2019/035753 A1 discloses a substrate structure that includes a dielectric layer, a first circuit layer, at least one conductive structure and a first protective layer. The first circuit layer is disposed adjacent to a first surface of the dielectric layer. The conductive structure includes a first portion and a second portion. The first portion is disposed on the first circuit layer. The first protective layer is disposed on the dielectric layer and contacts at least a portion of a sidewall of the first portion of the conductive structure. The first circuit layer and the conductive structure are integrally formed. US 2018/130759 A1 discloses a semiconductor package that includes a semiconductor substrate structure, a semiconductor die and an encapsulant. The semiconductor substrate structure includes a dielectric structure, a first patterned conductive layer, a first insulation layer and a conductive post. The first patterned conductive layer is embedded in the dielectric structure. The first insulation layer is disposed on the dielectric structure. The conductive post connects to the first patterned conductive layer and protrudes from the first insulation layer. The first insulation layer has a greater thickness at a position closer to the conductive post. The semiconductor die is electrically connected to the conductive post. The encapsulant covers the semiconductor die and at least a portion of the semiconductor substrate structure. WO 2020/009827 A1 discloses a substrate that that includes a first substrate portion, a second substrate portion and a second dielectric layer. The first substrate portion includes a core layer having a first core surface, and a plurality of core substrate interconnects, wherein the plurality of core substrate interconnects includes a plurality of surface core substrate interconnects formed over the first surface of core layer. The second substrate portion includes a first dielectric layer having a first dielectric surface, the first dielectric surface facing the first core surface of the core layer, and a plurality of substrate interconnects, wherein the plurality of substrate interconnects includes a plurality of interconnects formed over the first dielectric surface. The second dielectric layer is formed between the first substrate portion and the second substrate