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EP-4220699-B1 - FABRICATION METHOD FOR A DRAM STRUCTURE

EP4220699B1EP 4220699 B1EP4220699 B1EP 4220699B1EP-4220699-B1

Inventors

  • LU, JINGWEN

Dates

Publication Date
20260506
Application Date
20210924

Claims (13)

  1. A method of manufacturing a 1T-1C DRAM, comprising: providing a base (10, 20); forming a plurality of discrete first mask layers (11, 21) and a plurality of discrete second mask layers (12, 22) on the base (10, 20), wherein the first mask layers (11, 21) each extend along a first direction (X), the second mask layers (12, 22) each extend along a second direction (Y), the first direction (X) is different from the second direction (Y), the first mask layers (11, 21) intersect the second mask layers (12, 22), and the second mask layers (12, 22) each span a plurality of the first mask layers (11, 21); cutting off the first mask layers (11, 21) to form a plurality of discrete first sub-mask layers (118, 218), wherein the second mask layers (12, 22) each span a plurality of the first sub-mask layers (118, 218), and partial sidewalls of each of the first sub-mask layers (118, 218) are covered by the second mask layers (12, 22); etching the base (10, 20) through a first etching process by using the first sub-mask layers (118, 218) as a mask, to form discrete active regions (119); forming a isolation structure (13) located between adjacent active regions (119), and removing the first sub-mask layers (118, 218) not covered by the second mask layers (12, 22); and after a part of each of the first sub-mask layers (118, 218) is removed, etching the active regions (119) and the isolation structure (13) by using the second mask layers (12, 22) as a mask, to form a word line trench (16).
  2. The method of manufacturing a 1T-1C DRAM according to claim 1, wherein after a part of each of the first sub-mask layers (118, 218) is removed, the method further comprises: forming a third mask layer (15) on two opposite sidewalls of each of the second mask layers (12, 22); and forming the word line trench (16), comprising: etching the active regions (119) and the isolation structure (13) by using the second mask layers (12, 22) and the third mask layers (15) as a mask (15).
  3. The method of manufacturing a 1T-1C DRAM according to claim 2, wherein in a direction perpendicular to the second direction (Y), a ratio of a width of the second mask layer (12, 22) to a width of the third mask layer (15) is 4:1 to 6: 1.
  4. The method of manufacturing a 1T-1C DRAM according to claim 1, wherein forming the first mask layers (11) and the second mask layers (12) comprises: forming an initial first mask layer (111) on the base (10); forming discrete seventh mask layers (117) on the initial first mask layer (111), wherein the seventh mask layers (117) each extend along the first direction (X); forming a first sidewall layer (112) on each sidewall of the seventh mask layers (117); removing the seventh mask layers (117), and forming a second sidewall layer (113) on each sidewall of the first sidewall layers (112); removing the first sidewall layers (112), and etching the initial first mask layer (111) by using the second sidewall layers (113) as a mask, to form the first mask layers (11); forming an initial second mask layer (121) located between adjacent first mask layers (11); and patterning the initial second mask layer (121) by using a second etching process, to form the second mask layers (12).
  5. The method of manufacturing a 1T-1C DRAM according to claim 4, wherein an etching gas of the second etching process comprises O 2 and Ar.
  6. The method of manufacturing a 1T-1C DRAM according to claim 4, wherein the initial second mask layer (121) is also located on the first mask layers (11); and in a direction perpendicular to a top surface of the base (10), top surfaces of the second mask layers (12) are higher than top surfaces of the first mask layers (11).
  7. The method of manufacturing a 1T-1C DRAM according to claim 1, wherein forming the first sub-mask layers (118, 218) comprises: forming a fifth mask layer (191) on the first mask layers (11, 21), and patterning the fifth mask layer (191) to form discrete cutoff holes exposing the first mask layers (11, 21); and etching the first mask layers (11, 21) along the cutoff holes to form the first sub-mask layers (118, 218).
  8. The method of manufacturing a 1T-1C DRAM according to claim8, wherein the cutoff holes comprise first cutoff holes (193) and second cutoff holes (194); and for each of the first mask layers (11, 21), orthographic projections of the first cutoff holes (193) and the second cutoff holes (194) on a top surface of the first mask layer (11, 21) is alternately arranged; and forming the cutoff holes comprises: performing first patterning on the fifth mask layer (191) to form the first cutoff holes (193); forming a sixth mask layer (192) on the fifth mask layer (191) after the first cutoff holes (193) are formed, and patterning the sixth mask layer (192); and performing second patterning on the fifth mask layer (191) by using the patterned sixth mask layer (192) as a mask, to form the second cutoff holes (194).
  9. The method of manufacturing a 1T-1C DRAM according to claim 1, wherein forming the first sub-mask layers (118, 218) comprises: forming a fifth mask layer (191) on the first mask layers (11, 21), and patterning the fifth mask layer (191) to form second trenches (196) exposing the first mask layers (11, 21) and the second mask layers (12, 22); and etching the first mask layers (11, 21) by using the fifth mask layer (191) as a mask, to form the first sub-mask layers (118, 218).
  10. The method of manufacturing a 1T-1C DRAM according to claim 1, wherein the first etching process comprises plasma etching; according to the plasma etching, parts of the base (10, 20) are removed through ion beams; and the ion beams tilt 0° to 30° toward a bottom of the base (10, 20) along the first direction (X), to remove parts of the base (10, 20) located right below the second mask layers (12, 22).
  11. The method of manufacturing a 1T-1C DRAM according to claim 1, wherein an etch selectivity of the first etching process for the base (10, 20) and the second mask layers (12, 22) is greater than 10.
  12. The method of manufacturing a 1T-1C DRAM according to claim 1, wherein both the first mask layers (11, 21) and the second mask layers (12, 22) are hard mask layers.
  13. The method of manufacturing a 1T-1C DRAM according to claim 1, wherein after the word line trench (16) is formed, the method further comprises: forming a word line filling the word line trench (16).

Description

Technical Field The present disclosure relates to a method of manufacturing a 1T-1C DRAM. Background A dynamic random access memory (DRAM) is a type of semiconductor memory, which is widely used for computer systems and works mainly by using the presence or absence of charge stored in a capacitor to represent a binary bit. The DRAM generally includes structures such as a base, a word line and active regions. At present, the active regions are generally formed by using a self-aligned double patterning (SADP) technology. However, in the forming process, the active regions are prone to tilt or collapse, which may cause structural failure and reduce the yield of a semiconductor structure. Background art may be found in US2017/025420A1, US 2014/117566A1 and US 2015/333059A1 Summary The embodiments of the present disclosure provide a method of manufacturing a1T-1C DRAM. Brief Description of the Drawings The embodiments of the present disclosure are described in detail below with reference to the drawings. Those of ordinary skill in the art should understand that many technical details are proposed in the embodiments of the present disclosure to make the present application better understood. However, even without these technical details and various changes and modifications made based on the following embodiments, the technical solutions claimed in the present disclosure may still be realized. FIGS. 1 to 2 are schematic structural diagrams corresponding to various steps in a method of manufacturing a semiconductor structure;FIGS. 3 to 25 are schematic structural diagrams corresponding to various steps in a method of manufacturing a semiconductor structure according to an exemplary embodiment; andFIGS. 26 to 31 are schematic structural diagrams corresponding to various steps in a method of manufacturing a semiconductor structure according to an exemplary embodiment not forming part of the claimed invention. Detailed Description To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the following clearly and completely describes the technical solutions in the embodiments of the present disclosure with reference to the accompanying drawings in the embodiments of the present disclosure. Apparently, the described embodiments are some but not all of the embodiments of the present disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without creative efforts should fall within the protection scope of the present disclosure. It should be noted that the embodiments in the present disclosure and features in the embodiments may be combined with each other in a non-conflicting manner. A dynamic random access memory (DRAM) generally includes structures such as a base, a word line and active regions. The active regions are generally formed by using a self-aligned double patterning (SADP) technology. However, in the forming process, the active regions are prone to tilt or collapse, which may cause structural failure and reduce the yield of a semiconductor structure. Therefore, the yield of the semiconductor structure needs to be further improved. FIGS. 1 to 2 are schematic structural diagrams corresponding to various steps in a method of manufacturing a semiconductor structure. Referring to FIG. 1, a base 30 is provided and stripe-shaped first mask layers 31 are formed on the base 30. Referring to FIG. 2, the first mask layers 31 (referring to FIG. 1) are cut off to form a plurality of discrete first sub-mask layers 311, and the first sub-mask layers 311 are a mask layer to subsequently form active regions. The first sub-mask layers 311 are a plurality of discrete structures, and there are no other structures to fix and support the first sub-mask layers 311. Therefore, in an etching process, the first sub-mask layers 311 are prone to shift and tilt. Referring to FIG. 2, the base 30 is etched by using the first sub-mask layers 311 as a mask, to form the active regions. There is no structure to fix the first sub-mask layers 311 and the active regions, and there is a greater etching depth. Therefore, both the first sub-mask layers 311 and the active regions may collapse and tilt, thus reducing the yield of the semiconductor structure. The embodiments of the present disclosure provide a method of manufacturing a semiconductor structure, including: forming a plurality of discrete first mask layers and a plurality of discrete second mask layers on a base, wherein the first mask layers intersect the second mask layers, and each of the second mask layers spans a plurality of the first mask layers; cutting off the first mask layers to form a plurality of discrete first sub-mask layers, wherein the second mask layers each span a plurality of the first mask layers to achieve an effect of supporting and fixing the first mask layers, thus preventing the first sub-mask layers from displacement or tilt; etching the ba