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EP-4220700-B1 - MANUFACTURING METHOD OF MEMORY

EP4220700B1EP 4220700 B1EP4220700 B1EP 4220700B1EP-4220700-B1

Inventors

  • LIU, HAO
  • WAN, QIANG

Dates

Publication Date
20260506
Application Date
20210805

Claims (14)

  1. A manufacturing method of a1T-1C dram, comprising: providing a substrate; wherein the substrate comprises a core region (A) and a peripheral region (B) located outside the core region, a plurality of active regions (110) are arranged at intervals in the core region, and a first barrier layer (140) is further provided in the core region (S101); forming a first conductive layer (200) and a first mask layer (300) on the substrate in sequence (S102); etching the first mask layer (300), the first conductive layer (200), and the first barrier layer (140) which are in the core region (A), to form a first etched hole (310) penetrating through the first mask layer (300), the first conductive layer (200), and the first barrier layer (140); wherein the first etched hole (310) is opposite to the active region (S103); etching the substrate along the first etched hole (310), to form a bit line contact hole (150); wherein the bit line contact hole exposes (150) the active region (S104); removing the first mask layer (300) and the first conductive layer (200) which are in the core region and located around the bit line contact hole (150), and retaining the first barrier layer (140) located around the bit line contact hole (S105); and forming a bit line contact (410) in the bit line contact hole (150); wherein the bit line contact (410) is electrically connected to the active region (110), and a surface of the bit line contact (410) away from the substrate is flush with a surface of the first barrier layer (140) away from the substrate (S106); the manufacturing method of a 1T-1C dram being characterized in that it further comprises, after the step of forming a first conductive layer (200) and a first mask layer (300) on the substrate in sequence: forming a second mask layer (500), a third mask layer (600), and an intermediate layer (700) on the first mask layer in sequence; wherein the third mask layer in the core region has a filling hole penetrating through the third mask layer, and part of the intermediate layer is located in the filling hole (S201); removing part of the intermediate layer in the core region and the third mask layer in the core region, and retaining the intermediate layer located in the filling hole (S202); and removing, by taking the retained intermediate layer as a mask, the second mask layer exposed in the core region (S203).
  2. The manufacturing method of a 1T-1C dram according to claim 1, wherein the step of removing part of the intermediate layer (700) in the core region and the third mask layer (600) in the core region, and retaining the intermediate layer (700) located in the filling hole comprises: depositing a photoresist layer (800) on the intermediate layer (700) in the peripheral region, wherein the photoresist layer (800) covers the intermediate layer (700); removing, by taking the photoresist layer (800) as a mask, the intermediate layer (700) on the third mask layer (600) in the core region; and removing the third mask layer (600) in the core region and the photoresist layer (800) in the peripheral region, to expose the second mask layer (500) in the core region and the intermediate layer (700) in the peripheral region.
  3. The manufacturing method of a 1T-1C dram according to claim 2, wherein the third mask layer (600) comprises a first base layer (610) located on the second mask layer (500), and a first anti-reflection layer (620) located on the first base layer (610); and the step of removing the third mask layer (600) in the core region and the photoresist layer (800) in the peripheral region, to expose the second mask layer (500) in the core region and the intermediate layer (700) in the peripheral region, comprises: removing the first anti-reflection layer (620) in the core region, to expose the first base layer (610) in the core region; and removing the first base layer (610) in the core region and the photoresist layer (800) in the peripheral region at the same time.
  4. The manufacturing method of a 1T-1C dram according to claim 3, wherein an etch selectivity ratio of the first base layer (610) to the intermediate layer (700) is greater than or equal to 50; and when the first base layer (610) in the core region and the photoresist layer (800) in the peripheral region are etched and removed at the same time, a first etchant is oxygen, a first etching frequency is 60 MHz, and a first etching power is 1000 W to 1200 W.
  5. The manufacturing method of a 1T-1C dram according to claim 1, wherein the step of forming a second mask layer (500), a third mask layer (600), and an intermediate layer (700) on the first mask layer (300) in sequence comprises: depositing the second mask layer (500) and the third mask layer (600) on the first mask layer (300) in sequence; removing part of the third mask layer (600) in the core region, to form the filling hole; and depositing the intermediate layer (700) in the filling hole and on the third mask layer (600).
  6. The manufacturing method of a 1T-1C dram according to claim 1, wherein the second mask layer (500) comprises a second base layer (510) located on the first mask layer (300), and a second anti-reflection layer (520) located on the second base layer (510); and the step of removing, by taking a retained intermediate layer (700) as a mask, the second mask layer (500) exposed in the core region comprises: removing the second anti-reflection layer (520) exposed in the core region, and etching and removing part of the intermediate layer (700) in the core region and an entire intermediate layer (700) in the peripheral region; and etching the second base layer (510) by taking a remaining intermediate layer (700) as a mask, to remove an exposed second base layer (510).
  7. The manufacturing method of a 1T-1C dram according to claim 6, wherein an etch selectivity ratio of the intermediate layer (700) to the second anti-reflection layer (520) is 1, and a thickness of the intermediate layer (700) is less than 1.2 to 1.3 times a thickness of the second anti-reflection layer (520), such that the intermediate layer (700) is etched while the second anti-reflection layer (520) is etched.
  8. The manufacturing method of a 1T-1C dram according to claim 6, wherein when the second anti-reflection layer (520) exposed in the core region is etched and removed, and part of the intermediate layer (700) in the core region and the entire intermediate layer (700) in the peripheral region are etched and removed, a second etchant comprises sulfur hexafluoride and difluoromethane, and a diluent is nitrogen or helium.
  9. The manufacturing method of a 1T-1C dram according to claim 6, wherein the third mask layer (600) comprises a first base layer (610) located on the second mask layer (500), and a first anti-reflection layer (620) located on the first base layer (610); a thickness of the second base layer (510) is greater than or equal to 1.3 to 1.5 times a thickness of the first base layer (610); and an etch selectivity ratio of the second base layer (510) to the first anti-reflection layer (620) is greater than or equal to 20, such that at least part of the first anti-reflection layer (620) in the peripheral region is retained while the second base layer (510) is etched.
  10. The manufacturing method of a 1T-1C dram according to claim 6, wherein the third mask layer (600) comprises a first base layer (610) located on the second mask layer (500), and a first anti-reflection layer (620) located on the first base layer (610); and after the step of etching the second base layer (510) by taking a remaining intermediate layer (700) as a mask, to remove an exposed second base layer (510), the manufacturing method of a memory further comprises: removing the remaining intermediate layer (700), a remaining second anti-reflection layer (520) in the core region, and the first anti-reflection layer (620) in the peripheral region; and removing a remaining second base layer (510) in the core region and the first base layer (610) in the peripheral region at the same time.
  11. The manufacturing method of a 1T-1C dram according to claim 10, wherein an etch selectivity ratio of the first base layer (610) to the first mask layer (300) is greater than or equal to 50, and an etch selectivity ratio of the first base layer (610) to the second anti-reflection layer (520) is greater than or equal to 50; and when the remaining second base layer (510) in the core region and the first base layer (610) in the peripheral region are removed at the same time, a third etchant is oxygen, a second etching frequency is 60 MHz, and a second etching power is 1000 W to 1200 W.
  12. The manufacturing method of a 1T-1C dram according to claim 6, wherein the step of etching the first mask layer (300), the first conductive layer (200), and the first barrier layer (140) which are in the core region, to form a first etched hole (310) penetrating through the first mask layer (300), the first conductive layer (200), and the first barrier layer (140), wherein the first etched hole (310) is opposite to the active region (110) comprises: etching the first mask layer (300), the first conductive layer (200), and the first barrier layer (140) by taking the remaining intermediate layer (700) as a mask, to form the first etched hole (310).
  13. The manufacturing method of a 1T-1C dram according to claim 12, wherein the step of removing the first mask layer (300) and the first conductive layer (200) in the core region and located around the bit line contact hole (150), and retaining the first barrier layer (140) located around the bit line contact hole (150) further comprises: removing a remaining first mask layer (300) and a remaining first conductive layer (200) in the core region, and removing the second anti-reflection layer (520) in the peripheral region; and removing the second base layer (510) in the peripheral region, to expose the first mask layer (300) in the peripheral region.
  14. The manufacturing method of a 1T-1C dram according to claim 1, wherein the step of forming a bit line contact (410) in the bit line contact hole (150) comprises: depositing a second conductive layer (400) in the bit line contact hole (150), on the first barrier layer (140) in the core region, and on the first mask layer (300) in the peripheral region; removing the second conductive layer (400) on the first barrier layer (140) in the core region and the second conductive layer (400) in the peripheral region; and removing the first mask layer (300) in the peripheral region, to expose the first conductive layer (200) in the peripheral region.

Description

Technical Field The present application relates to the technical field of semiconductors, and in particular, to a manufacturing method of a 1T-1C dram. Background With gradual development of storage device technologies, a dynamic random access memory (DRAM) is widely used in various electronic devices due to its high density and fast reading/writing speed. A DRAM usually includes a plurality of memory cells. Each memory cell includes a transistor and a capacitor. A gate of the transistor is electrically connected to a word line, a source of the transistor is electrically connected to a bit line, and a drain of the transistor is electrically connected to the capacitor. A word line voltage on the word line can control on or off of the transistor, such that data information stored in the capacitor can be read through the bit line or data information can be written to the capacitor. During manufacturing of a memory, a void or a seam is easily formed within a bit line contact, resulting in performance degradation of the memory. Background may be found in US2019/355728A1, US 2015/241771A1 and US 2018/342520A1. Summary Embodiments of the present application provide a manufacturing method of a 1T-1C dram. The invention is set out in the appended set of claims. Brief Description of the Drawings FIG. 1 is a schematic structural diagram after formation of a bit line contact in the related art;FIG. 2 is a flowchart of a manufacturing method of a memory according to an embodiment of the present application;FIG. 3 is a schematic structural diagram of a substrate according to an embodiment of the present application;FIG. 4 is a schematic structural diagram of a core region after formation of a first mask layer according to an embodiment of the present application;FIG. 5 is a schematic structural diagram of a core region after formation of a first etched hole according to an embodiment of the present application;FIG. 6 is a schematic structural diagram of a core region after formation of a bit line contact hole according to an embodiment of the present application;FIG. 7 is a schematic structural diagram of a core region after removal of part of a first conductive layer and part of a first mask layer according to an embodiment of the present application;FIG. 8 is a schematic structural diagram of a core region after formation of a bit line contact according to an embodiment of the present application;FIG. 9 is a schematic structural diagram after removal of part of a first conductive layer and part of a first mask layer according to an embodiment of the present application;FIG. 10 is a schematic structural diagram after formation of a second conductive layer according to an embodiment of the present application;FIG. 11 is a schematic structural diagram after removal of part of a second conductive layer according to an embodiment of the present application;FIG. 12 is a schematic structural diagram after removal of the remaining first mask layer according to an embodiment of the present application;FIG. 13 is a flowchart of after formation of a first mask layer according to an embodiment of the present application;FIG. 14 is a schematic structural diagram after formation of a first photoresist layer according to an embodiment of the present application;FIG. 15 is a schematic structural diagram after removal of part of an intermediate layer in a core region according to an embodiment of the present application;FIG. 16 is a schematic structural diagram after etching of a first anti-reflection layer in a core region according to an embodiment of the present application;FIG. 17 is a schematic structural diagram after etching of a first base layer in a core region according to an embodiment of the present application;FIG. 18 is a schematic structural diagram after etching of a second anti-reflection layer in a core region according to an embodiment of the present application;FIG. 19 is a schematic structural diagram after etching of a second base layer in a core region according to an embodiment of the present application;FIG. 20 is a schematic structural diagram after formation of a first etched hole according to an embodiment of the present application;FIG. 21 is a schematic structural diagram after removal of the remaining intermediate layer in a core region according to an embodiment of the present application;FIG. 22 is a schematic structural diagram after removal of the remaining second base layer in a core region according to an embodiment of the present application; andFIG. 23 is a schematic structural diagram after removal of a second anti-reflection layer in a peripheral region according to an embodiment of the present application. Detailed Description The inventor of the present application found in actual work that, referring to FIG. 1, during deposition of a second conductive layer 400, a bit line contact 410 is formed in the second conductive layer 400 located in a bit line contact hole, and a void or a seam easily