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EP-4243079-B1 - SEMICONDUCTOR DEVICE, INTEGRATED CIRCUIT, AND ELECTRONIC DEVICE

EP4243079B1EP 4243079 B1EP4243079 B1EP 4243079B1EP-4243079-B1

Inventors

  • JIAO, Chunkun

Dates

Publication Date
20260506
Application Date
20230306

Claims (15)

  1. A semiconductor device comprising: • an n-type semiconductor substrate (6); • a drift layer (5), wherein the drift layer (5) is disposed on a surface of the semiconductor substrate (6); • a semiconductor layer (2), wherein the semiconductor layer (2) is disposed on a surface that is of the drift layer (5) and that is away from the semiconductor substrate (2), and comprises a source region (21) and a well region (23), the source region (21) is an n-type semiconductor region, and the source region (21) is exposed on a side that is of the semiconductor layer (2) and that is away from the drift layer (5); • a groove (4), wherein an opening of the groove (4) is located on a surface that is of the semiconductor layer (2) and that is away from the drift layer (5), a gate (41) is disposed in the groove (4), and a gate oxide layer (42) is disposed between the gate (41) and a surface of the groove (4); • a p-type shielding structure (81(8), 82(8)), wherein the shielding structure (81(8), 82(8)) is disposed at the drift layer (5) and is used to protect the gate oxide layer (42) at the bottom of the groove (4), wherein the well region (23) is separately in contact with the shielding structure (81(8), 82(8)) and the source region (21) and a depth of the shielding structure (81(8), 82(8)) is greater than a depth of the groove (4), wherein the shielding structure (81(8), 82(8)) comprises a plurality of first shielding structures (81(8)) and a plurality of second shielding structures (82(8)), each of the first shielding structures (81(8)) extends in a first direction, each of the second shielding structures (82(8)) extends in a second direction, the first direction intersects with the second direction and the first direction and the second direction are located in a plane parallel to the surface of the semiconductor substrate (6), and the plurality of first shielding structures (81(8)) and the plurality of second shielding structures (82(8)) are disposed in a grid shape, wherein each of the plurality of the first shielding structures (81(8)) and each of the plurality of the second shielding structures (82(8)) comprises a first shielding portion (84) and a second shielding portion (85), ∘ wherein the first shielding portion (84) extends in a fifth direction, and the fifth direction is perpendicular to the first direction and the second direction, and the first shielding portion (84) has at least one side facing the gate oxide layer (42), o the second shielding portion (85) is located at an end portion of a side that is of the first shielding portion (84) and that faces the semiconductor substrate (6), and the second shielding portion (85) extends in a direction parallel to the surface of the semiconductor substrate (6) to form a protruding edge of the first shielding portion (84); • a source (1) disposed on the side that is of the semiconductor layer (6) and that is away from the drift layer (5), and in contact with the source region (21) and a gate insulation layer (3); and • a drain (7) disposed on a side that is of the semiconductor substrate (6) and that is away from the drift layer (5).
  2. The semiconductor device according to claim 1, wherein the first shielding structure is bar-shaped, and the plurality of first shielding structures are parallel to each other and arranged at spacings of a first specified distance; and the second shielding structure is bar-shaped, and the plurality of second shielding structures are parallel to each other and arranged at spacings of a second specified distance.
  3. The semiconductor device according to claim 1 or 2, wherein the groove comprises a plurality of first grooves and a plurality of second grooves, the first groove extends in a third direction, the second groove extends in a fourth direction, the third direction intersects with the fourth direction, and the plurality of first grooves and the plurality of second grooves are disposed in a grid shape.
  4. The semiconductor device according to claim 3, wherein the first direction is the same as the third direction, and the second direction is the same as the fourth direction.
  5. The semiconductor device according to claim 4, wherein at least one of the first shielding structures is disposed between any two adjacent first grooves, and at least one of the second shielding structures is disposed between any two adjacent second grooves.
  6. The semiconductor device according to any one of claims 1 to 5, wherein the first direction is perpendicular to the second direction.
  7. The semiconductor device according to any one of claims 1 to 6, wherein the semiconductor layer further comprises a first semiconductor region , wherein the first semiconductor region is a p-type semiconductor region, and the well region is also a p-type semiconductor region; the well region is in contact with the shielding structure, the source region, and the first semiconductor region, and the first semiconductor region is further in contact with the source; and a doping concentration of the first semiconductor region is greater than a doping concentration of the shielding structure.
  8. The semiconductor device according to claim 7, wherein an orthographic projection of the first semiconductor region on the semiconductor substrate coincides with an orthographic projection of an overlapping region between the first shielding structure and the second shielding structure on the semiconductor substrate.
  9. The semiconductor device according to claim 7, wherein an orthographic projection of the first semiconductor region on the semiconductor substrate coincides with an orthographic projection of the shielding structure on the semiconductor substrate.
  10. The semiconductor device according to any one of claims 7 to 9, wherein a doping concentration of the well region is less than the doping concentration of the first semiconductor region.
  11. The semiconductor device according to any one of claims 1 to 10, further comprising a current spreading layer, wherein the current spreading layer is an n-type semiconductor region, the current spreading layer is located at the drift layer and adjacent to the semiconductor layer, and a distance between the semiconductor substrate and a surface that is of the current spreading layer and that faces the semiconductor substrate is less than a distance between the semiconductor substrate and a surface that is of the groove and that faces the semiconductor substrate.
  12. The semiconductor device according to any one of claims 1 to 11, wherein a distance between the semiconductor substrate and a surface that is of the shielding structure and that faces the semiconductor substrate is less than the distance between the semiconductor substrate and the surface that is of the groove and that faces the semiconductor substrate.
  13. The semiconductor device according to any one of claims 1 to 12, wherein the shielding structure is symmetrically disposed on a peripheral side of the groove.
  14. An integrated circuit comprising a circuit board and the semiconductor device according to any one of claims 1 to 13 that is disposed on the circuit board.
  15. An electronic device comprising a housing and the integrated circuit according to claim 14, wherein the integrated circuit is disposed in the housing.

Description

TECHNICAL FIELD This application relates to the field of semiconductor technologies, and in particular, to a semiconductor device, an integrated circuit, and an electronic device. BACKGROUND Compared with Si materials, SiC materials have advantages such as a wide band gap, a high critical breakdown electric field, a high thermal conductivity, and a high electron saturation drift velocity. Compared with an insulated gate bipolar transistor (IGBT) made of Si, a metal-oxide-semiconductor field-effect transistor (MOSFET) made of SiC has features such as a high breakdown voltage and a low conduction voltage drop. In addition, due to a unipolar conduction feature, the SiC MOSFET has a higher switching speed, a lower conduction loss, and a lower switching loss than the Si IGBT. Therefore, the SiC MOSFET has replaced the Si IGBT in some fields. For example, US 10 937 901 B2 refers to: injection control regions of a second conductivity type provided on a charge transport region of a first conductivity type; Main electrode regions of the first conductivity type provided on the injection control regions; insulated gate electrode structures going through the main electrode region and the injection control regions in the depth direction; an injection suppression region going through the main electrode regions and the injection control regions in the depth direction so as to form a pn junction in a path leading to the charge transport region, the injection suppression region including a semiconductor material with a narrower bandgap than a material of the charge transport region; and a contact protection region of the second conductivity type contacting the bottom surface of the injection suppression region. Further, US 2020/373292 Al refers to a semiconductor device having first second-conductivity-type high-concentration regions, second second-conductivity-type high-concentration regions, third second-conductivity-type high-concentration regions, and fourth second-conductivity-type high-concentration regions. The first connecting regions each connect a portion of each of the first second-conductivity-type high-concentration regions and a portion of each of the second second-conductivity-type high-concentration regions. The second connecting regions each connect a portion of each of the third second-conductivity-type high-concentration regions and a portion of each of the fourth second-conductivity-type high-concentration regions. A ratio of a mathematical area of the first connecting regions to a mathematical area of the second second-conductivity-type high-concentration regions is greater than a ratio of a mathematical area of the second connecting regions to a mathematical area of the fourth second-conductivity-type high-concentration regions. Further, US 2020/303540 Al refers to an insulated-gate semiconductor device including: a carrier transport layer of a first conductivity-type made of a semiconductor material having a wider band gap than silicon; a lower buried region of a second conductivity-type buried in an upper portion of the carrier transport layer; a plurality of upper buried regions of the second conductivity-type dispersedly deposited on the lower buried region; an injection control region of the second conductivity-type deposited on the upper buried regions; and an insulated gate structure controlling a surface potential of the injection control region adjacent to a side wall of a trench, wherein the trench has a stripe-like shape, the lower buried region includes a first stripe provided separately from the trench, and the respective upper buried regions are provided at intervals on the first stripe. Further, US 10 700 182 B2 refers to determining, by using at least one of a processor device and model transistor cells, a set of design parameters for at least one of a transistor cell and a drift structure of a wide band-gap semiconductor device, wherein an on state failure-in-time rate and an off state failure-in-time rate of a gate dielectric of the transistor cell are within a same order of magnitude for a predefined on-state gate-to-source voltage, a predefined off-state gate-to-source voltage, and a predefined off-state drain-to-source voltage. In comparison with a conventional planar gate MOSFET, a size of a unit cell of the MOSFET may be reduced in a groove gate MOSFET. In this case, density of unit cells of a chip is increased, thereby increasing channel density and improving a through-current capability. The groove gate MOSFET can be used to significantly reduce an on resistance of a device. However, in the groove gate MOSFET, a gate oxide layer is prone to cause electric field concentration at the bottom of or at a corner of a groove. Consequently, the gate oxide layer is broken down at a voltage lower than a rated voltage. This greatly affects a blocking feature of the device. Therefore, providing a solution for reducing the electric field concentration of the gate oxide layer at the bottom o