EP-4243086-B1 - DUAL WIDTH FINFET

Inventors

• LIU, QING

Dates

Publication Date

20260513

Application Date

20150908

Claims (5)

1. A FinFET, comprising: a silicon substrate having an oxide layer (118) buried therein: a raised epitaxial silicon source region (144) overlying the silicon substrate and having a diamond-shape profile; a raised epitaxial silicon drain region (144) overlying the silicon substrate and having a diamond-shape profile; a strained silicon fin (120) having, as a first portion, a channel region that extends between the raised source and drain regions, the channel region having a first fin width (126), a second fin portion in the source region, the second fin portion having a second fin width (142), and a third fin portion in the drain region, the third fin portion having a third fin width (142); and a metal gate structure (130) that wraps around at least three sides of the strained silicon fin to control current flow in the channel region, wherein the third fin portion is substantially equal in width to the second fin portion and the second fin portion is smaller than the channel region, wherein the fin has the same height along the first fin portion, the second fin portion and the third fin portion, and wherein the strained silicon fin includes as dopants one or more of arsenic (As), boron (B), and phosphorous (P), and the portions of the fin outside the channel region exhibit a uniform distribution of dopants.
2. The FinFET of claim 1 wherein the channel region has a width in a range of 6 - 12 nm and the second portion has a width less than 5 nm.
3. The FinFET of claim 1 wherein in the raised source and drain regions, the strained silicon fin has an aspect ratio in a range of 5 - 10.
4. The FinFET of claim 1 wherein the strained silicon fin includes one or more of silicon (Si), silicon germanium (SiGe), or silicon carbide (SiC).
5. The FinFET of claim 1 wherein the metal gate structure includes sidewall spacers made of one or more of silicon nitride (SiN) or SiBCN.

Description

BACKGROUND Technical Field The present disclosure generally relates to advanced transistor structures for use in integrated circuits. Description of the Related Art Advanced integrated circuits typically feature strained channel devices, silicon-on-insulator substrates, FinFET structures, or combinations thereof, in order to continue scaling transistor gate lengths below 20 nm. Such technologies allow the channel length of the transistor to shrink while minimizing detrimental consequences such as current leakage and other short channel effects. A FinFET is an electronic switching device that features a conducting channel in the form of a semiconducting fin that extends outward from the substrate surface. In such a device, the gate, which controls current flow in the fin, wraps around three sides of the fin so as to influence current flow from three surfaces instead of one. The improved control achieved with a FinFET design results in faster switching performance in the "on" state and less current leakage in the "off" state than is possible in a conventional planar device. Incorporating strain into the channel of a semiconductor device stretches the crystal lattice, thereby increasing charge carrier mobility in the channel so that the device becomes a more responsive switch. Introducing compressive strain into a PFET transistor tends to increase hole mobility in the channel, resulting in a faster switching response to changes in voltage applied to the transistor gate. Likewise, introducing a tensile strain into an NFET transistor tends to increase electron mobility in the channel, also resulting in a faster switching response. There are many ways to introduce strain into the channel region of a FinFET. Techniques for introducing strain typically entail incorporating into the device epitaxial layers of one or more materials having crystal lattice dimensions or geometries that differ slightly from those of the silicon substrate. The epitaxial layers can be made of doped silicon or silicon germanium (SiGe), for example. Such epitaxial layers can be incorporated into source and drain regions, or into the transistor gate that is used to modulate current flow in the channel, or into the channel itself, which is the fin. Alternatively, strain can be induced in the fin from below the device by using various types of silicon-on-insulator (SOI) substrates. An SOI substrate features a buried insulator, typically a buried oxide layer (BOX) underneath the active area. SOI FinFET devices have been disclosed in patent applications assigned to the present assignee, for example, U.S. Patent Application No. 14/231,466, entitled "SOI FinFET Transistor with Strained Channel," U.S. Patent Application No. 14/588,116, entitled "Silicon Germanium-on-insulator FinFET," and U.S. Patent Application No. 14/588,221, entitled "Defect-Free Strain-Relaxed Buffer. US2012/115284 A1 discloses a FinFET having raised source/drain regions formed on a fin that has been thinned where exposed by the gate. The raised source/drain regions impart strain to the channel. BRIEF SUMMARY A dual width SOI FinFET having a strained channel and raised source and drain regions is disclosed, along with a method of fabrication. In fabricating strained FinFET devices, especially those having short channels less than about 20 nm in length, one challenge that arises is forming a very narrow semiconducting fin without inadvertently relieving strain in the fin material. Subjecting the fin to a subtractive process such as reactive ion etching (RIE) removes material by a combination of mechanical and chemical mechanisms wherein the mechanical aspect imparts destructive kinetic energy to the crystal lattice of the fin. The present inventors have observed that such a process tends to relax strain in the crystal lattice, whereas wet etching is a purely chemical process that alters the lattice more gently, thus having the potential to maintain strain. However, wet etching has the constraint that it is an isotropic process lacking in directional control. The invention is defined in independent claim 1. Preferred embodiments are defined in the dependent claims. A fabrication method is disclosed in which lateral recess of a strained fin in the source and drain regions is accomplished using a wet chemical etching process so as to maintain a high degree of strain in the fin while trimming the fin width in the source and drain regions to less than 5 nm. The resulting FinFET features a wider fin underneath the gate, and a narrower fin in the source and drain regions. An advantage of the narrower fin is that it can be more easily doped during the growth of the epitaxial raised source and drain regions. According to an aspect, a FinFET, comprises: a silicon substrate having an oxide layer buried therein;a raised epitaxial silicon source region overlying the silicon substrate;a raised epitaxial silicon drain region overlying the silicon substrate;a strained silicon fin having, as a f