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EP-4254803-B1 - DIGITAL ISOLATOR

EP4254803B1EP 4254803 B1EP4254803 B1EP 4254803B1EP-4254803-B1

Inventors

  • DESSARD, VINCENT

Dates

Publication Date
20260506
Application Date
20190709

Claims (5)

  1. A digital isolator (10) comprising: - a logic module circuit (20) arranged to receive a digital signal D, and to generate corresponding first (41) and second (42) command signals, wherein the logic module circuit (20) is referenced to a first ground G1; - a first sawtooth modulator circuit (51) referenced to the first ground G1 and arranged to receive the first command signal (41), and in response generate a first sawtooth signal at a first node A1, wherein the first sawtooth signal has a fast rising edge followed by a slow falling edge when the digital signal equals 1, and the first sawtooth signal has a fast falling edge followed by a slow rising edge when the digital signal equals 0; - a second sawtooth modulator circuit (52) referenced to the first ground G1 and arranged to receive the second command signal (42), and in response generate a second sawtooth signal at a second node A2, wherein the second sawtooth signal has a fast falling edge followed by a slow rising edge when the digital signal equals 1, and a fast rising edge followed by a slow falling edge when the digital signal equals 0; and - a first isolation capacitor (61) coupled to the first sawtooth modulator circuit (51) at the first node A1 and to a first input terminal of an output circuit at a third node B1; and - a second isolation capacitor (62) coupled to the second sawtooth modulator circuit (52) at the second node A2 and to a second input terminal of the output circuit at a fourth node B2; wherein the output circuit is referenced to a second ground G2 and is arranged to generate an output signal OUT corresponding to the digital signal D, wherein a fast rising edge has a higher rate of signal change with respect to time than a slow rising edge, and wherein a fast falling edge has a higher rate of signal change with respect to time than a slow falling edge, the digital isolator (10) further comprising a first impedance element (101) coupled between the third node B1 and a bias voltage source (110) referenced to the second ground G2 and a second impedance element (102) coupled between the fourth node B2 and the bias voltage source (110) wherein the output circuit comprises a first comparator (121) having a first input connected to the third node B1 and a second input connected to the fourth node B2, wherein the first comparator (121) is arranged to generate a logical 1 output when a voltage at its first input exceeds a voltage at its second input by a first threshold, and a logical 0 output otherwise and wherein the output circuit comprises a second comparator (122) having a first input connected to the fourth node B2 and a second input connected to the third node B1, wherein the second comparator (122) is arranged to generate a logical 1 output when a voltage at its first input exceeds a voltage at its second input by a second threshold, and a logical 0 output otherwise.
  2. The digital isolator (10) of claim 1, wherein durations of slow rising edges and/or of slow falling edges at the first and second nodes are at least two times durations of corresponding fast falling edges and/or fast rising edges, respectively.
  3. The digital isolator (10) of claim 1, wherein a clock signal having a period T0 has a pulse width shorter than T0/3.
  4. The digital isolator (10) of claim 1, wherein the logic module circuit (20) comprises means for disabling a clock generator (30) at a transition of the digital signal, and to reenabling the clock generator (30) after a delay TD.
  5. The digital isolator (10) of claim 4, wherein delay TD is larger than 0.5*T0, 0.6*T0, 0.7*T0 ,0.8*T0 or T0.

Description

Field of the invention The present invention generally relates to the field of capacitive isolation links. The invention relates to the field of capacitive isolation systems for use in isolating electrical circuits from one another while transmitting digital information data. More particularly, this invention relates to isolation systems having capacitor-coupled isolation barriers. This is useful in, for example, industrial process control application, telephony, medical electronics, data communication. Description of prior art Isolators are generally implemented to separate circuits or circuit sections of the electrical circuit to one another from undesired influence of, as for example but not limiting, other circuits or circuit sections, to minimize the influence of common mode transients (CMT), influence of radiation or electromagnetic interferences, cross talk, between circuits or circuit sections. Capacitive isolation links are also used to minimize the transmission of interferences introduced by the environment from one circuit to another or from one section of a circuit to one another. It is also used in galvanic isolation, to isolate high voltages from one another or to isolate low voltage command circuits to high voltage power circuits. Capacitive isolation links also allow better integration compared to other systems based for example on electromagnetic isolators. Capacitive isolation links usually make use of a dielectric in order to block direct current between isolated circuits sections of the electrical circuits or to block lowest-frequency currents between the circuits sections while allowing transfer of a higher frequency data signal. The isolation barrier usually includes one or more capacitors or transformers. For this reason, information data shape commonly used is square signals with very fast transients used for the edges of the signal followed by a maintained information level (no transient information) allowing to transmit only the edge variation of the signal through the capacitive barrier. Nevertheless, common mode transients (CMT) may be caused either as a result of different supply voltages and grounds that are present at different circuits or circuits sections or as the result of external interferences such as for example, radiation, electromagnetic fields, temperature variation. As a consequence, high frequency transients can corrupt the data transmission of a data signal across the isolation barrier. It is well known that addressing the effect of the CMT in a digital isolator is a challenge in designing such digital isolators. Document SLLA284A "Digital Isolator Design Guide" from Texas Instrument, discloses capacitive isolation link devices including at least two data channels: a high-frequency channel (HF) with a bandwidth generally from 100kbps up to 150Mbps, and a low-frequency channel (LF) covering the range below down to dc. In principle, a single-ended input signal entering the HF-channel is split into a differential signal via the inverter gate at the input. The following capacitor-resistor networks differentiate the signal into small and narrow transients, which then are converted into rail-to-rail differential pulses by two comparators. The comparator outputs drive a NOR-gate flip-flop whose output feeds an output multiplexer. A decision logic (DCL) at the driving output of the flip-flop measures the durations between signal transients. If the duration between two consecutive transients exceeds a certain time limit (as in the case of a low-frequency signal) the DCL forces the output-multiplexer to switch from the high-frequency to the low-frequency channel. Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus creating a sufficiently high frequency, capable of passing the capacitive barrier. As the input is modulated, a low-pass filter (LPF) is needed to remove the high-frequency carrier from the actual data before passing it on to the output multiplexer. Document US2017/0302225A1 discloses a system where the input circuit includes an on-off keying (OOK) modulator configured to generate a modulated data signal in response to the input data signal and the carrier signal. The output circuit includes a frequency shift keying (FSK) demodulator configured to detect a presence of the carrier signal in the modulated differential data signal and generate a demodulated data signal in response to the presence of the carrier signal. Document EP0973305A1 discloses a capacitive insulating barrier system with a sawtooth signal as a carrier to generate a Pulse Width Modulation (PWM) signal as an input signal of the capacitive insulation barrier. There are two capacitors between input and output circuit which provide isolation between input and output circuits. A square pulse width modulated signal is used as transmitted signal f