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EP-4261651-B1 - LOW DROP-OUT REGULATOR CIRCUIT, CORRESPONDING DEVICE AND METHOD

EP4261651B1EP 4261651 B1EP4261651 B1EP 4261651B1EP-4261651-B1

Inventors

  • CONTE, ANTONINO
  • RUTA, MARCO
  • TOMAIUOLO, FRANCESCO
  • PISASALE, MICHELANGELO
  • GRIMAL, Marion Helne

Dates

Publication Date
20260506
Application Date
20230331

Claims (13)

  1. A circuit, comprising: an output node (vout) configured to apply an output voltage to a load (Cload), an input comparator (10) configured to perform a comparison of a reference voltage (vref) and a voltage (vfb) that is a function (LC) of the output voltage and to produce a comparison signal (COMP_OUT) having a first logical value or a second logical value based on the outcome of the comparison, and driver circuitry (12A, 12B) coupled to the input comparator (10) to receive the comparison signal (COMP_OUT) therefrom, the driver circuitry comprising at least one driver transistor (MDRV_1A, MCASC_2A, MDRV_1B, MCASC_2B) having a current flow path therethrough coupled to the output node (vout) and a control terminal (B1, C1, B2, C2) configured to receive a voltage-pumped (100A; vbl_boost) replica of the comparison signal (COMP_OUT), wherein said replica of the comparison signal (COMP_OUT) has a first respective logical value or a second respective logical value based on the outcome of the comparison at the input comparator (10), wherein the current flow path through the least one driver transistor (MDRV_1A, MCASC_2A, MDRV_1B, MCASC_2B) is conductive or non-conductive in response to the voltage-pumped (100A, vbl_boost) replica of said comparison signal (COMP_OUT) having the first respective logical value or the second respective logical value, wherein the driver circuitry comprises a first (12A) and a second (12B) driver coupled to the input comparator (10) to receive the comparison signal (COMP_OUT) therefrom and each of the first (12A) and second (12B) drivers comprises: at least one driver transistor (MDRV _1A, MCASC_2A, MDRV_1B, MCASC_2B) having a current flow path therethrough coupled to the output node (vout) and a control terminal (B1, C1, B2, C2), voltage boost capacitive circuitry (C1A, C1B, C2A, C2B) configured to apply to the control terminal (B1, C1, B2, C2) of the at least one driver transistor (MDRV_1A, MCASC_2A, MDRV_1B, MCASC_2B) said voltage-pumped (100A; vbl_boost) replica of the comparison signal (COMP_OUT), voltage refresh transistor circuitry (M1A, M2A, M1B, M2B) coupled to the voltage boost capacitive circuitry (C1A, C1B, C2A, C2B) to transfer thereon said voltage-pumped (100A, vbl_boost) replica of the comparison signal (COMP_OUT), wherein the first (12A) and second (12B) drivers are controllably (PA_LV, PB_LV) switchable between: a first mode of operation during which the current flow path through the least one driver transistor (MDRV _1A, MCASC_2A, MDRV_1B, MCASC_2B) is conductive or non-conductive in response to the voltage-pumped (100A; vbl_boost) replica of said comparison signal (COMP_OUT) having the first respective logical value or the second respective logical value and the voltage refresh transistor circuitry (M1A, M2A, M1B, M2B) is deactivated (OFF), and a second mode of operation during which the voltage refresh transistor circuitry (M1A, M2A, M1B, M2B) coupled to the voltage boost capacitive circuitry (C1A, C1B, C2A, C2B) is activated (ON) to transfer thereon said voltage-pumped (100A; vbl_boost) replica of the comparison signal (COMP_OUT), so that the current flow path through the at least one driver transistor (MDRV_1A, MCASC_2A, MDRV_1B, MCASC_2B) is non-conductive.
  2. The circuit of claim 1, comprising mode control circuitry (100A) configured (PA_LV, PB_LV) to alternately switch the first (12A) and second (12B) drivers between: a first operating condition wherein the first driver (12A) is in the first mode of operation and the second driver (12B) is in the second mode of operation, and a second operating condition wherein the first driver (12A) is in the second mode of operation and the second driver (12B) is in the first mode of operation.
  3. The circuit of claim 2, wherein the mode control circuitry (100A) is configured (PA_LV, PB_LV) to switch the first (12A) and second (12B) drivers to a transition operating condition wherein both the first driver (12A) and the second driver (12B) are in the first mode of operation.
  4. The circuit of any of the previous claims, wherein each of the first (12A) and second (12B) drivers comprises a current flow line between a supply node (vcc) and the output node (vout) comprising the cascaded arrangement of current flow paths through: a first driver transistor (MDRV_1A, MDRV_1B) having the current flow path therethrough coupled to the output node (vout), a second driver transistor (MCASC_2A, MCASC_2B) arranged with the current flow path therethrough between the supply node (vcc) and the first driver transistor (MDRV_1A, MDRV_1B).
  5. The circuit of claim 4, wherein the first driver transistor (MDRV_1A, MDRV_1B) and the second driver transistor (MCASC_2A, MCASC_2B) are low-voltage and high-voltage transistors, respectively.
  6. The circuit of claim 4 or claim 5, comprising mode control circuitry (100A) configured (EN) to switch the first (12A) and second (12B) drivers to an off condition wherein the output node (vout) is grounded and the second driver transistor (MCASC_2A, MCASC_2B) in both the first (12A) and second (12B) drivers is non-conductive.
  7. The circuit of any of the previous claims, wherein each of the first (12A) and second (12B) drivers comprises: a circuit node (A1, A2) configured (N1, N2) to have applied thereto the comparison signal (COMP_OUT), first (C1A, C2A) and second (C1B, C2B) voltage boost capacitors arranged with said circuit node (A1, A2) intermediate therebetween, a first voltage refresh transistor (M1A, M1B) having a current flow path therethrough arranged between the first voltage boost capacitor (C1A, C2A) and the output node (vout), and a second voltage refresh transistor (M2A, M2B) having a cu rrent flow path therethrough arranged between the second boost capacitor (C1B, C2B) and a boosted voltage supply node (vbl_boost).
  8. The circuit of claim 7, insofar as depending on any of claims 4 to 6, wherein each of the first (12A) and second (12B) drivers comprises: the first driver transistor (MDRV _1A, MDRV_1B) having a control terminal coupled to the current flow path through the first refresh transistor (M1A, M1B) between (B1, B2) the first refresh transistor (M1A, M1B) and the first voltage boost capacitor (C1A, C2A); and the second driver transistor (MCASC_2A, MCASC_2B) having a control terminal coupled to the current flow path through the second refresh transistor (M2A, M2B) between (C1, C2) the second refresh transistor (M2A, M2B) and the boosted voltage supply node (vbl_boost).
  9. The circuit of claim 8, wherein each of the first (12A) and second (12B) drivers comprises the control terminal of the second driver transistor (MCASC_2A, MCASC_2B) being coupled to the current flow path through the second refresh transistor (M2A, M2B) via a transistor switch (M3A, M4A, M3B, M4B) configured to be made non-conductive to decouple the control terminal of the second driver transistor (MCASC_2A, MCASC_2B) from the current flow path through the second refresh transistor (M2A, M2B) in response to the circuit being disabled (EN = 0).
  10. A device comprising: a circuit according to any of the preceding claims, and an electrical load (Cload) coupled to said output node (vout) in the circuit to receive a regulated voltage therefrom.
  11. A method of operating a circuit according to any of claims 1 to 9, or a device according to claim 10, the method comprising alternately switching (PA_LV, PB_LV) the first (12A) and second (12B) drivers between: a first operating condition wherein the first driver (12A) is in the first mode of operation and the second driver (12B) is in the second mode of operation, and a second operating condition wherein the first driver (12A) is in the second mode of operation and the second driver (12B) is in the first mode of operation.
  12. The method of claim 11, comprising switching (PA_LV, PB_LV) the first (12A) and second (12B) drivers to a transition operating condition wherein both the first driver (12A) and the second driver (12B) are in the first mode of operation.
  13. The method of claim 12, wherein switching (PA_LV, PB_LV) the first (12A) and second (12B) drivers to said transition operating condition comprises: discontinuing the second mode of operation in one (12A, resp. 12B) of the first and second drivers deactivating the voltage refresh transistor circuitry (M1A, M2A, M1B, M2B) therein while maintaining the other (12B, resp. 12A) of the first and second drivers in the first mode of operation, wherein both of the first (12A) and second (12B) are in the first mode of operation, and discontinuing the first mode of operation in the other (12A, resp. 12B) of the first and second drivers activating the voltage refresh transistor circuitry (M1A, M2A, M1B, M2B) therein.

Description

Technical field The description relates to low drop-out (LDO) regulators. The examples described herein can be applied, for instance, in battery-operated products such as portable devices of small size. Description of the related art The designation low drop-out (LDO) regulator denotes a DC voltage regulator capable of regulating an output voltage even if the input or supply voltage lies in the vicinity of the output voltage. LDO regulators are widely used for industrial and automotive applications. The increasing demand for portable and battery-operated products have forced these circuits to operate over a wide range of supply voltage and multi-voltage platforms. As a consequence, standby and quiescent current flow are major concerns considering also that these regulators are expected to operate in a wide temperature range (-40°C to 125°C, typically). Documents such as: Tang Junyao ET AL: "A 0.7V Fully-on-Chip Pseudo-Digital LDO Regulator with 6.3[yog]A Quiescent Current and 100mV Dropout Voltage in 0.18-[yog]m CMOS", 31 December 2018 (2018-12-31), pages 1-4;US 2020/144913 A1;WANG XIAOYANG ET AL: "A Dynamically High-Impedance Charge-Pump-Based LDO With Digital-LDO-Like Properties Achieving a Sub-4-fs FoM", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE, USA, vol. 55, no. 3, 30 December 2019 (2019-12-30), pages 719-730; orWO2020/053879 A1 are exemplary of background information in the area of the invention. Object and summary An object of one or more embodiments is to contribute in adequately addressing the issues discussed in the foregoing. According to one or more embodiments, such an object is achieved via a circuit having the features set forth in claim 1 that follows. One or more embodiments relate to a corresponding device as per claim 10. A portable, battery-operated product of small size for consumer or professional electronics is exemplary of such a device. One or more embodiments relate to a corresponding method as per claim 11. The claims are an integral part of the technical teaching provided herein in respect of the embodiments. In examples presented herein an on/off output stage is used for an LDO driven with a propagation time of few hundreds of picoseconds thanks to the use of a cascoded structure. This is driven by shifting capacitors refreshed in a way that allows a response that is completely uncorrelated to the refresh clock frequency. A level shifter and a charge pump of conventional type are no longer needed for such an arrangement. Examples presented herein adopt an output driver having a response time comparable with the response time of a low-voltage (LV) comparator; a corresponding LDO will thus exhibit an improved response time. Examples presented herein involve voltage shifting that takes place thanks to a pulse on the bottom plate of a charged capacitor. Short pulses of the LV comparator are not filtered, which improves the efficiency of the LDO. Examples presented herein include a (very) small boost pump: this is used only to refresh small boost capacitors and not the gate of an output driver; area and current consumption are reduced because inefficiency introduced by a small pump is negligible. Examples presented herein include two drivers (collectively, "driver circuitry") that are symmetrical and work in alternance: when one driver is in a pulsing phase the other driver is in a refreshing phase and vice-versa. An overlapped phase is contemplated in which both drivers are pulsing, to facilitate continued regulation. Examples presented herein include a phase generator that, starting from a refreshing clock, generates signals to manage different operation phases of the main drivers. In examples as presented herein, the response time of the output driver is comparable with the response time of a low-voltage (LV) comparator; the LDO will thus exhibit improved response time performance. Brief description of the figures One or more embodiments will now be described, by way of example only, with reference to the annexed figures, wherein: Figure 1 is a circuit diagram of a conventional low drop-out (LDO) regulator,Figure 2 represents a boost pump and a phase generator for use in a circuit as discussed herein,Figure 3 is diagram exemplary of a circuit as discussed herein, andFigures 4 to 7 are illustrative of possible operating conditions of a circuit according to the diagram of Figure 3. Unless otherwise indicated, corresponding numerals and symbols in the different figures generally refer to corresponding parts. Also, throughout this description, a same designation may be used for brevity to designate: a certain node or line as well as a signal occurring at that node or line, anda certain component (e.g., a capacitor or a resistor) as well as an electrical parameter thereof (e.g., capacitance or resistance/impedance). Detailed description In the ensuing description, various specific details are illustrated in order to provide an in-depth understanding of various examples of embodiments