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EP-4266358-B1 - SEMICONDUCTOR DEVICE

EP4266358B1EP 4266358 B1EP4266358 B1EP 4266358B1EP-4266358-B1

Inventors

  • LEE, DOOHYUN
  • SHIN, HEONJONG
  • KIM, SEONBAE
  • PARK, JINYOUNG
  • PARK, HYUNHO
  • YU, Jimin
  • JANG, JAERAN

Dates

Publication Date
20260506
Application Date
20230127

Claims (15)

  1. A semiconductor device, comprising: a substrate (101); active regions (105) extending in a first horizontal direction on the substrate, wherein the active regions comprise a first active region (105a) and a second active region (105b) spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction, and a third active region (105c) and a fourth active region (105d) spaced apart from each other in the second horizontal direction; gate structures (160) comprising a first gate structure (160a), a second gate structure (160b), a third gate structure (160c), and a fourth gate structure (160d), wherein the first gate structure (160a) and the second gate structure (160b) intersect the first active region (105a) and the second active region (105b) and are spaced apart from each other in the first horizontal direction, and wherein the third gate structure (160c) and the fourth gate structure (160d) intersect the third active region (105c) and the fourth active region (105d) and are spaced apart from each other in the first horizontal direction; source/drain regions (150) comprising a first source/drain region (150a) on the first active region (105a) between the first gate structure (160a) and the second gate structure (160b), a second source/drain region (150b) on the second active region (105b) between the first gate structure (160a) and the second gate structure (160b), a third source/drain region (150c) on the third active region (105c) between the third gate structure (160c) and the fourth gate structure (160d), and a fourth source/drain region (150d) on the fourth active region (105d) between the third gate structure (160c) and the fourth gate structure (160d); contact plugs (170) comprising a first contact plug (170a) connected to the first source/drain region (150a), a second contact plug (170b) connected to the second source/drain region (150b), a third contact plug (170c) connected to the third source/drain region (150c), and a fourth contact plug (170d) connected to the fourth source/drain region (150d); a first isolation insulating pattern (181) between the first contact plug (170a) and the second contact plug (170b); and a second isolation insulating pattern (182) between the third contact plug (170c) and the fourth contact plug (170d), wherein a first length (L1) in a vertical direction of the first isolation insulating pattern (181) is smaller than a second length (L2) in the vertical direction of the second isolation insulating pattern (182), wherein the vertical direction is perpendicular to an upper surface of the substrate (101).
  2. The semiconductor device of claim 1, wherein the first isolation insulating pattern (181) separates the first contact plug (170a) and the second contact plug (170b) from each other and is in contact with each of the first contact plug (170a) and the second contact plug (170b), and wherein the second isolation insulating pattern (182) separates the third contact plug (170c) and the fourth contact plug (170d) from each other and is in contact with each of the third contact plug (170c) and the fourth contact plug (170d).
  3. The semiconductor device of claim 1 or 2, wherein an average width of the first isolation insulating pattern (181) is smaller than an average width of the second isolation insulating pattern (182) in the second horizontal direction.
  4. The semiconductor device of claim 1, 2 or 3, wherein a lower surface of the first isolation insulating pattern (181) is at a level higher than a level of a lower surface of each of the source/drain regions, and wherein a lower surface of the second isolation insulating pattern (182) is at a level lower than the level of the lower surface of each of the source/drain regions.
  5. The semiconductor device of any preceding claim, wherein the first isolation insulating pattern (181) is spaced apart from the source/drain regions, and wherein the second isolation insulating pattern (182) contacts the source/drain regions.
  6. The semiconductor device of any preceding claim, wherein each of the gate structures comprises a gate electrode extending in one direction, a spacer structure extending in the one direction on both sidewalls of the gate electrode, and a capping layer on the gate electrode and the spacer structure, wherein the first isolation insulating pattern (181) is spaced apart from the spacer structure of each of the gate structures, and wherein the second isolation insulating pattern (182) contacts the spacer structure of each of the gate structures.
  7. The semiconductor device of claim 6, wherein the second isolation insulating pattern (182) contacts the gate electrode of each of the gate structures.
  8. The semiconductor device of any preceding claim, wherein the first isolation insulating pattern (181) comprises a first side surface having a first slope in the first horizontal direction, a second side surface having a second slope in the first horizontal direction different from the first slope, and a third side surface having a third slope in the second horizontal direction, wherein the second isolation insulating pattern (182) comprises side surfaces in the first horizontal direction and the second horizontal direction, and wherein slopes of the side surfaces of the second isolation insulating pattern (182) are substantially equal to each other.
  9. The semiconductor device of any preceding claim, wherein the first contact plug (170a) and the second contact plug (170b) have a width increasing toward the substrate in the second horizontal direction, and wherein the third contact plug (170c) and the fourth contact plug (170d) have a width that is decreasing toward the substrate (101) or is constant in the second horizontal direction.
  10. The semiconductor device of any preceding claim, wherein each of the first contact plug (170a) and the second contact plug (170b) comprises an extension portion extending to a region between the source/drain regions and the first isolation insulating pattern (181).
  11. The semiconductor device of any preceding claim, further comprising: a third isolation insulating pattern (183) extending in the first horizontal direction, wherein the third isolation insulating pattern (183) penetrates through a plurality of adjacent gate structures among the gate structures, wherein the third isolation insulating pattern (183) and the second isolation insulating pattern (182) comprise a same material, and wherein the third isolation insulating pattern (183) has a length in the vertical direction, substantially equal to the second length of the second isolation insulating pattern (182).
  12. The semiconductor device of any preceding claim, further comprising: a fourth isolation insulating pattern (184), wherein the fourth isolation insulating pattern (184) encloses, on a plane, a plurality of adjacent active regions among the active regions and a plurality of gate structures intersecting the plurality of adjacent active regions, wherein the plurality of gate structures intersecting the plurality of adjacent active regions are adjacent to each other among the gate structures, wherein the fourth isolation insulating pattern (184) and the second isolation insulating pattern (182) comprise a same material, and wherein the fourth isolation insulating pattern (184) has a length in the vertical direction, substantially equal to the second length of the second isolation insulating pattern (182).
  13. The semiconductor device of any preceding claims, : wherein the first isolation insulating pattern (181) is spaced apart from the first source/drain region (150a) and the second source/drain region (150b), and wherein the second isolation insulating pattern (182) contacts the third source/drain region (150c) and the fourth source/drain region (150d).
  14. The semiconductor device of claim 13, wherein a lower surface of the first isolation insulating pattern (181) is on a level higher than a level of a lower surface of the second isolation insulating pattern (182).
  15. The semiconductor device of claim 13 or 14, wherein the first isolation insulating pattern (181) comprises a plurality of side surfaces having different slopes, and wherein the second isolation insulating pattern (182) comprises side surfaces having one slope.

Description

BACKGROUND Example embodiments of the disclosure relate to a semiconductor device. As the demand for high performance, high speed, and/or multifunctionality of a semiconductor device has increased, integration density of a semiconductor device has also increased. In manufacturing a semiconductor device having a fine pattern corresponding to the trend of high integration of the semiconductor device, it has been necessary to implement patterns having a fine width or a fine spacing. Also, to address the limitations of operation properties due to the size reduction of a planar metal oxide semiconductor FET (MOSFET), there have been attempts to develop a semiconductor device including a FinFET having a three-dimensional channel structure. US 2020/105603 A1, US 2020/119180 A1 and US 10,121,702 B1 describe related semiconductor devices. SUMMARY The invention provides a semiconductor device as set out in the accompanying claims. BRIEF DESCRIPTION OF DRAWINGS The above and other aspects, features, and advantages of certain embodiments of the disclosure will be more apparent from the following detailed description, taken in combination with the accompanying drawings, in which: FIG. 1 is a plan diagram illustrating a semiconductor device according to an example embodiment;FIGS. 2A to 2C are cross-sectional diagrams illustrating a semiconductor device according to an example embodiment;FIG. 3 is a cross-sectional diagram illustrating a semiconductor device according to an example embodiment;FIG. 4 is a cross-sectional diagram illustrating a semiconductor device according to an example embodiment;FIG. 5 is a cross-sectional diagram illustrating a semiconductor device according to an example embodiment;FIG. 6 is a cross-sectional diagram illustrating a semiconductor device according to an example embodiment;FIGS. 7A and 7B are cross-sectional diagrams illustrating a semiconductor device according to an example embodiment;FIG. 8 is a plan diagram illustrating a semiconductor device according to an example embodiment; andFIGS. 9A to 9C, 10A, 10B, 11A, 11B, 12A, 12B, 13A, and 13B are diagrams illustrating processes of a method of manufacturing a semiconductor device according to an example embodiment. DETAILED DESCRIPTION Hereinafter, embodiments of the disclosure will be described as follows with reference to the accompanying drawings. It will be understood that when an element or layer is referred to as being "over," "above," "on," "below," "under," "beneath," "connected to" or "coupled to" another element or layer, it can be directly over, above, on, below, under, beneath, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly over," "directly above," "directly on," "directly below," "directly under," "directly beneath," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. Like numerals refer to like elements throughout. Spatially relative terms, such as "over," "above," "on," "upper," "below," "under," "beneath," "lower," and the like, may be used herein for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the term "below" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. For the sake of brevity, conventional elements to semiconductor devices may or may not be described in detail herein for brevity purposes. FIG. 1 is a plan diagram illustrating a semiconductor device 100 according to an example embodiment. FIGS. 2A and 2C are cross-sectional diagrams illustrating a semiconductor device 100 according to an example embodiment. FIG. 2A is a cross-sectional diagram illustrating a semiconductor device 100 taken along line I-I' in FIG. 1, FIG. 2B is a cross-sectional diagram illustrating a semiconductor device 100 taken along line II-II' in FIG. 1, and FIG. 2C is a cross-sectional diagram illustrating a semiconductor device 100 taken along line III-III' in FIG. 1. Only main components of the semiconductor device are illustrated in FIGS. 1 to 2C for ease of description. Referring to FIGS. 1 to 2C, the semiconductor device 100 may include a substrate 101, active regions 105 on the substrate 101, device isolation layers 107 isolating the active regions 105 from each other, a plurality of channel layers 140 disposed