EP-4272080-B1 - DATA STORAGE CIRCUIT

Inventors

• EICKEL, Karl Heinz

Dates

Publication Date

20260506

Application Date

20220321

Claims (11)

1. Data storage circuit comprising a plurality of configuration registers (CONFIG_REG_i) provided to store configuration data (WRDATAIN (31...0)), an error detection unit arranged to detect errors in the configuration data (WRDATAIN (31...0)) after storing configuration data (WRDATAIN (31...0)) in the respective configuration register (CONFIG_REG_i) and/or when checking the stored configuration data (WRDATAIN (31...0)) from the respective configuration register (CONFIG_REG_i), wherein a plurality of error detection units in form of parity checkers each being arranged to detect errors by checking in each cycle the configuration data and related parity bit read out of the respective configuration register are provided, wherein each configuration register (CONFIG_REG_i) is connected to a respective error detection unit to form pairs of related functional units for parity check, or wherein a set of the same bit positions in the configuration registers (CONFIG_REG_i) is connected to a respective error detection unit to form pairs of related functional units for parity check.
2. Data storage circuit according to claim 1, comprising a parity generation unit (Parity_GEN_i) provided to generate a parity bit (P) for configuration data (WRDATAIN (31...0)), wherein the data storage circuit is arranged to store the generated parity bit (P) together with a related configuration data (WRDATAIN (31...0)) in the respective configuration register (CONFIG_REG_i), wherein the error detection units are arranged to read out the stored parity bit (P) and the related configuration data (WRDATAIN (31...0)), to recalculate the parity bit (P) for the read out configuration data (DOUT (31...0)) and to compare the stored parity bit (P) with the recalculated parity bit (P) in order to detect an error in the read out configuration data (DOUT (31...0)) or the read out parity bit (P).
3. Data storage circuit according to claim 1 or 2, wherein the error detection units are arranged to detect errors by use of an error correction code.
4. Data storage circuit according to claim 1, wherein each error detection unit comprises - a parity generation unit (Parity_GEN_i) provided to generate a parity bit (P) for a set of the bits in the same positions of the set of configuration registers (CONFIG_REG_i), - a parity bit (P) storage unit provided to store a respective parity bit (P) generated by the related parity generation unit (Parity_GEN_i), - a parity check unit (Parity_CHECK) for comparing the parity bit (P) generated by the parity generation unit (Parity_GEN_i) and the stored parity bit (P) previously generated and stored in the parity bit storage unit in order to detect an error in the configuration data (WRDATAIN (31...0)).
5. Data storage unit according to claim 4, wherein the data storage circuit is arranged to store the parity bit (P) generated by the parity generation unit (Parity_GEN_i) in the respective parity bit storage unit once in a write cycle directly after all configuration registers (CONFIG_REG_i) or a part of the configuration registers (CONFIG_REG_i) have been written with configuration data (WRDATAIN (31...0)).
6. Data storage unit according to claim 5, wherein a clock gate (CG1) is provided to generate a clock signal (clk_par) from a system clock signal (sys_clock) and a configuration end signal (CEND) at the input of the clock gate (CG1), and a configuration end register (CEND_REG) is provided to store the configuration end signal (CEND) for exact one cycle.
7. Data storage circuit according to one of claims 4, 5 or 6, wherein the parity bit storage unit is formed by a Flip-Flop (FFi) provided for the set of error detection units.
8. Data storage circuit according to one of the preceding claims, wherein each error detection unit provides an error flag (PERR_i) at the output of each of the error detection units.
9. Data storage circuit according to claim 8, wherein each error detection unit provides an error flag (PERR_i) at the output of each of the error detection units only if a configuration active signal (CACT) is inactive, wherein an active configuration active signal (CACT) indicates a running write cycle and an inactive configuration active signal (CACT) indicates a termination of a write cycle.
10. Data storage circuit according to claim 9, wherein an AND-gate (&) is provided to disable the provision of error flags (PERR_i) during configuration.
11. Data storage circuit according to one of the preceding claims, wherein the configuration registers (CONFIG_REG_i) comprise a configuration clock input (clk_cfg) to allow writing of control data into the respective configuration register (CONFIG_REG_i), wherein a clock gate (CG2) is provided to generate said clock signal (clk_cfg) from a system clock signal (sys_clock) and a configuration active signal (CACT) at the input of the clock gate (CG2), and wherein a configuration active register (CACT_REG) is provided to store the configuration active signal (CACT) for an intended write cycle.

Description

The invention relates to a data storage circuit comprising a plurality of configuration registers provided to store configuration data, an error detection unit arranged to detect errors in the configuration data after storing configuration data in the respective configuration register and/or when checking the stored configuration data from the respective configuration register. Memories and registers must be protected according to ISO standard 26262 against permanent and transient faults in safety critical applications. Therefore, it has been the state of the art for many years to implement safety mechanisms to detect and report such faults. US 8,766,662 B1 discloses a method and a system for operating a programmable device, including accessing a master summary data and loading an original configuration data to configuration registers of the programmable device. Current summary data are generated by performing a summary operation of a current configuration data of the configuration registers of the programmable device, comparing the current summary data with the master summary data, and performing an exception action if the current summary data does not match with the master summary data. EP 0 013 885 B1 discloses a method for preventing undesired parity error signal in a parity check of a register. The data field in a register is provided to store a data byte including the related parity bit. In order to provide a more flexible method, the register field has an associated parity bit latch arrangement with one respective further parity bit position for a register into which, prior to the parity check, a digital bit is read in. In contrast to registers that only store data temporarily, configuration registers are usually only written once and configure important functions in their system on a chip (SoC). Therefore, errors that occur in these configuration registers would have fatal consequences regarding functional safety according to ISO 26262. In a system on a chip, registers are normally written with data via a system bus. If these registers are to be protected, a parity bit is generated via the write data and the register is expanded by this parity bit, which is written into the register with the write data. When reading the register, the read out data and the read out parity bit are checked by a parity checker. An error signal PERR is set for each one-bit error that occurs in the register data or the parity bit that has been read. US 2021/0303393 A1 discloses an Ethernet PHY device comprising a serial communication interface adapted to be coupled to a microcontroller, a register set having registers, and a checksum generator circuit coupled to the register set and configured to calculate a current checksum. The embodiment also includes a checksum register that is coupled to the checksum generator and is configured to store the current checksum. It further includes a checksum checker that is coupled to the checksum generator, the checksum register and the microcontroller, and is configured to compare a previous value of the checksum to the current checksum and, responsive to the previous value being different than the current checksum, send an error report to the microcontroller. The embodiment also includes a trigger circuit coupled to the checksum generator configured to send a checksum start signal to the checksum generator. The checksum is checked in runtime after registration of a picture in the register set. The aim of the present invention is to provide an improved data storage circuit allowing to detect multiple faults in a configuration register due to a hardware fault or due to an unintended write of the configuration register. The object is achieved by the data storage circuit comprising the features of claim 1. Preferred embodiments are described in the dependent claims. According to the present invention, a plurality of error detection units in form of parity checkers each being arranged to detect errors by checking in each cycle the configuration data and related parity bit read out of the respective configuration register are provided, wherein each configuration register is connected to a respective error detection unit to form pairs of related functional units for parity check, or wherein a set of the same bit positions in the configuration registers is connected to a respective error detection unit to form pairs of related functional units for parity check. In case that a parity bit generated for respective configuration data is written into a configuration register together with the related configuration data, an error detection unit is connected downstream of each configuration register. The register data and the read out parity bit are checked in each cycle by the related error detection unit (parity checker). An error signal is set for each one-bit error that occurs in the register or the parity bit that has been read. This allows to recognise occurring errors automatically in real t