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EP-4290521-B1 - ENHANCED DATA CLOCK OPERATIONS IN MEMORY

EP4290521B1EP 4290521 B1EP4290521 B1EP 4290521B1EP-4290521-B1

Inventors

  • SUH, JUNGWON
  • CHUN, DEXTER TAMIO
  • LO, MICHAEL HAWJING
  • THOZIYOOR, SHYAMKUMAR
  • KUMAR, RAVINDRA

Dates

Publication Date
20260506
Application Date
20200228

Claims (15)

  1. A memory (150), comprising; a memory array (162); a memory I/O module (160) configured to receive a data clock from a host (110) via a link and output an internal data clock, wherein the internal data clock is in synchronization with the data clock from the host (110), and wherein the memory (150) is configured to read from the memory array (162) or write to the memory array /162) based on the toggling of the internal data clock; and a command decoder (173) configured to detect a data clock suspend command while the internal data clock is synchronized with the data clock from the host (110), wherein the data clock suspend command comprises operands of WS_WR and WS_FS at logic one and WS_RD at logic zero, and wherein the internal data clock is configured to disable toggling in response to the command decoder (173) detecting the data clock suspend command; the command decoder (173) is further configured to detect a read or write command subsequent to detecting the data clock suspend command, and the internal data clock is further configured to start toggling based on the data clock from the host in response to the command decoder (173) detecting the read or write command.
  2. The memory (150) of claim 1 is configured to perform a read or write operation in response to the read or write command.
  3. The memory (150) of claim 1 further comprises a memory mode register (170) configured to store information of the data clock suspend command, wherein the information of the data clock suspend command preferably indicates whether the memory supports the data clock suspend command.
  4. The memory (150) of claim 1, wherein the memory I/O module (160) is configured to receive the toggling of the data clock after receiving the data clock suspend command.
  5. The memory (150) of claim 1, wherein the internal data clock is coupled to the data clock by a clock buffer, wherein the clock buffer is preferably configured to be disabled to disable the toggling of the internal data clock.
  6. An apparatus (100), comprising: a host (110) coupled to a memory (150) as defined in claim 1 via a link (190), wherein the host (110) is configured to synchronize a data clock from the host (110) with an internal data clock of the memory (150) and to output write data or capture read data based on the internal data clock, wherein the host (110) comprises a memory controller (130) configured to provide a data clock suspend command to the memory (150) via the link (190) while the internal data clock is synchronized between the host (110) and the memory (150), wherein the data clock suspend command notifies the memory (150) to disable toggling the internal data clock, the internal data clock being configured to toggle based on the data clock from the host (110), wherein the data clock suspend command comprises operands of WS_WR and WS_FS at logic one and WS_RD at logic zero, to toggle the data clock after providing the data clock suspend command, to provide a read or write command to the memory (150) via the link (190), subsequent to providing the data clock suspend command, wherein the read or write command notifies the memory (150) to start toggling the internal data clock, and to provide the read or write command to access the memory(150), without performing synchronization of the internal data clock and the data clock from the host between providing the data clock suspend command and providing the read or write command.
  7. The apparatus (100) of claim 6, wherein the memory controller (130) is configured to provide a mode register read command to the memory via the link, for information of the data clock suspend command, and configured to provide the data clock suspend command based on the information of the data clock suspend command, wherein the information of the data clock suspend command preferably indicates whether the memory supports the data clock suspend command.
  8. The apparatus (100) of claim 6, wherein the memory controller (130) is configured to operate in accordance with a low power double data rate dynamic random-access memory specification.
  9. The apparatus (100) of claim 8, , wherein the memory preferably comprises an LPDDR5 memory, wherein the read or write command is preferably between a first time period and a second time period after the data clock suspend command.
  10. A method to reduce power of an internal data clock for a memory coupled to a host via a link, comprising: receiving (710) a data clock from a host, by the memory, via the link; synchronizing (720), by the memory, the internal data clock with the data clock from the host; toggling (730), by the memory, the internal data clock based on the data clock from the host to capture write data or to output read data; detecting (740), by the memory, a data clock suspend command while the internal data clock is synchronized between the memory and the host, wherein the data clock suspend command comprises operands of WS_WR and WS_FS at logic one and WS_RD at logic zero; disabling (750) toggling of the internal data clock based on the data clock from the host, in response to detecting the data clock suspend command; detecting (760), by the memory, a read or write command subsequent to detecting the data clock suspend command; starting (770) toggling the internal data clock based on the data clock from the host in response to detecting the read or write command; and performing (780) a read or write operation, by the memory, in response to the read or write command.
  11. The method of claim 10, further comprising storing, by a memory mode register, information of the data clock suspend command, wherein the information of the data clock suspend command preferably indicates whether the memory supports the data clock suspend command.
  12. A method, comprising: providing (810), by a host to a memory via a link, a data clock from the host to a memory, wherein the memory is configured to toggle an internal data clock based on the data clock from the host to capture write data or to output read data; providing (820), by the host to the memory via the link, a data clock suspend command, while the internal data clock is synchronized between the host and the memory, wherein the data clock suspend command comprises operands of WS_WR and WS_FS at logic one and WS_RD at logic zero, and wherein the memory is configured to disable toggling of the internal data clock in response to the data clock suspend command; and providing (840), by the host to the memory via the link, a read or write command after the data clock suspend command, wherein the memory is configured to start toggling the internal data clock in response to the read or write command and to perform the read or write operation in response to the read or write command.
  13. The method of claim 12 further comprising: providing, by the host to the memory via the link, a mode register read command; and receiving, from the memory by the host via the link, information of the data clock suspend command in response to the mode register read command, wherein the information of the data clock suspend command indicates whether the memory supports the data clock suspend command.
  14. The method of claim 12 further comprising determining, by the host, whether to providing, the data clock suspend command to the memory based on types, numbers, timing of commands, or instructions stored in a memory access queue module.
  15. The method of claim 12, wherein providing the read or write command after the data clock suspend command is between a first time period and a second time period after providing the data clock suspend command, preferably further comprising providing, by the host to the memory via the link, a command to instruct the memory to exit a data clock synchronization after providing the read or write command, wherein providing the command to instruct the memory to exit a data clock synchronization is preferably done if a next read or write command is longer than the second time period of a previous read or write command.

Description

Field The present disclosure relates generally to methods and apparatuses having enhanced data clock operations and more particularly, to methods and apparatuses having a data clock suspend mode to reduce power consumption while a data clock is in an always-on mode. Background A computing device (e.g., a laptop, a mobile phone, etc.) may include one or several processors to perform various functions, such as telephony, wireless data access, and camera/video function, etc. A memory is an important component of the computing device. The one processor may be couple to the memory to perform the aforementioned computing functions. For example, the one processor may fetch instructions from the memory to perform the computing function and/or to store within the memory temporary data for processing these computing functions, etc. The memory may be embedded with the one processor on a semiconductor die or be part of a different semiconductor die. The memory may perform various functions. For example, the memory may be used as cache, register file, or storage. The memory may be of various kinds. For example, the memory may be static random access memory (SRAM), dynamic random access memory (DRAM), magnetic random access memory (MRAM), NAND flash, or NOR flash, etc. As demands grow for the computing device to perform more functions with increasing speed, power issue grows as well. While power savings may be of particular interest in mobile computing devices, non-mobile devices may also benefit from reduced power consumption to reduce waste heat generation. Thus, computing devices of various sorts may benefit from memory systems that have decreased power consumption. Schemes to reduce power consumer are thus desirable. Attention is drawn to document US 2017/0004869 A1 which relates to a semiconductor memory device which includes a command decoder configured to generate an auto-sync signal in response to a command for writing data at a memory cell or reading data from a memory cell, and an internal data clock generating circuit configured to phase synchronize a second clock, having a clock frequency higher than a clock frequency of a first clock, with the first clock in response to the auto-sync signal. Furthermore attention is drawn to document WO 2018/081746 A1 which relates to a memory subsystem which triggers entry and exit of a memory device from low power mode with a chip select (CS) signal line. For a system where the command bus has no clock enable (CKE) signal line, the system can trigger low power modes with CS instead of CKE. The low power mode can include a powerdown state. The low power mode can include a self-refresh state. The memory device includes an interface to the command bus, and receives a CS signal combined with command encoding on the command bus to trigger a low power mode state change. The memory device can be configured to monitor the CS signal and selected other command signals while in low power mode. The system can send an ODT trigger while the memory device is in low power mode, even without a dedicated ODT signal line. Attention is also drawn to document US 2003/189868 A1 which relates to methods and devices for a memory system. A digital memory device can receive power-down commands during the pendency of an active-mode command such as a burst read or write, that is, "early". The device shuts down some circuitry, such as address and command registers, immediately upon receipt of the early power-down command. Other device components, e.g., those involved in servicing the burst read or write, remain active at least until their portion of the command has been completed. In some embodiments, the early power-down command can be issued concurrently with an active-mode command as an option to that command, freeing a memory controller from having to schedule and issue power-down commands separately. WO 2017/011351 A1 relates to methods, apparatus, and system for use in adaptive communication interfaces are disclosed. An adaptive communication interface is provided, in which a high-speed clock provided in a high-speed mode of operation is suppressed in a low-power mode of operation. In the low-power mode of operation, a low-speed command clock is used for data transfers between a memory device and a system-on-chip, applications processor or other device. A method for operating the adaptive communication interface may include using a first clock signal to control transmissions of commands to a memory device over a command bus. In a first mode of operation, the first clock signal controls data transmissions over the adaptive communication interface. In a second mode of operation, the second clock signal controls data transmissions over the adaptive communication interface. The frequency of the second clock signal may be greater than the frequency of the first clock signal. Finally, attention is drawn to document Mt46h32m16lf: "Mobile Low-Power DDR SDRAM", 1 January 2014. SUMMARY The invention is de