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EP-4312265-B1 - ARRAY SUBSTRATE AND METHOD FOR PREPARING SAME, AND DISPLAY PANEL

EP4312265B1EP 4312265 B1EP4312265 B1EP 4312265B1EP-4312265-B1

Inventors

  • WANG, XIAOYUAN
  • WANG, WU
  • FANG, YAN
  • WU, Shengxue

Dates

Publication Date
20260506
Application Date
20191218

Claims (9)

  1. An array substrate, comprising a base (10); a pixel electrode (50) and a thin film transistor, disposed on the base (10); a passivation layer (16), covering the thin film transistor and the pixel electrode (50), the passivation layer (16) being provided with a transferring through hole (K1,K2) exposing the pixel electrode (50) and a drain electrode (15) or a source electrode (14) of the thin film transistor simultaneously; a connection electrode (60), disposed on the passivation layer (16) and at the transferring through hole (K1,K2), wherein the connection electrode (60) is connected with the pixel electrode (50), and the drain electrode (15) or the source electrode (14) through the transferring through hole (K1,K2) , wherein the array substrate further comprises a gate line (30) and a data line (40), wherein the thin film transistor comprises a gate electrode (11), an active layer (13), the source electrode (14) and the drain electrode (15), the pixel electrode (50), the gate line (30) and the gate electrode (11) are disposed on the base (10), the pixel electrode (50), the gate line (30) and the gate electrode (11) are covered with a gate insulation layer (12), the active layer (13), the source electrode (14), the drain electrode (15) and the data line (40) are disposed on the gate insulation layer (12), and a conductive channel is formed between the source electrode (14) and the drain electrode (15), characterized in that : the connection electrode (60) comprises a first compensation block (60A) which is a portion of the connection electrode (60) disposed at a side of the connection electrode (60) close to the gate line (30), an orthographic projection of the first compensation block (60A) on the base (10) overlaps at least a portion of an orthographic projection of an edge of the drain electrode (15) or the source electrode (14) at a side adjacent to the gate line (30) on the base (10), and the first compensation block (60A) extends from a main body of the connection electrode (60) towards the gate line (30), and in a plane which is parallel to the substrate, a size of the first compensation block (60A) are smaller than a size of the main body in a direction parallel to a direction of the gate line (30); and the connection electrode (60) comprises a second compensation block (60B) which is another portion of the connection electrode (60) disposed at a side of the connection electrode (60) away from the gate line (30), an orthographic projection of the second compensation block (60B) on the base (10) overlaps at least a portion of an orthographic projection of an edge of the source electrode (14) or the drain electrode (15) at a side away from the gate line (30) on the base (10), the second compensation block (60B) extends from the main body of the connection electrode (60) to a direction away from the gate line (30), in a plane which is parallel to the substrate, a size of the second compensation block (60B) is smaller than a size of the main body in a direction parallel to a direction of the gate line (30), wherein shapes of the first compensation block and/or the second compensation block comprises a rectangle, a trapezoid, a semicircle or a semi-ellipse.
  2. The array substrate according to claim 1, wherein an orthographic projection of the transferring through hole (K1,K2) on the base (10) overlaps with an orthographic projection of the pixel electrode (50) on the base (10) and an orthographic projection of the drain electrode (15) or the source electrode (14) on the base (10).
  3. The array substrate according to claim 1, wherein an orthographic projection of the connection electrode (60) on the base (10) covers an orthographic projection of an overlapped region between the drain electrode (15) or the source electrode (14) and the pixel electrode (50) on the base (10).
  4. The array substrate according to any one of claims 1-3, wherein the transferring through hole (K1,K2) comprises a first through hole portion (K1) and a second through hole portion (K2), the first through hole portion (K1) exposes the drain electrode (15), the second through hole portion (K2) exposes the pixel electrode (50).
  5. A display panel comprising the array substrate according to any one of claims 1-4.
  6. A manufacturing method of an array substrate, comprising: forming a pixel electrode (50) and a thin film transistor; forming a passivation layer (16) covering the thin film transistor, the passivation layer (16) being provided with a transferring through hole (K1,K2) that exposes the pixel electrode (50) and a drain electrode (15) or a source electrode (14) of the thin film transistor simultaneously; forming a connection electrode (60) on the passivation layer (16) and at the transferring through hole (K1,K2), wherein the connection electrode (60) is simultaneously connected with the pixel electrode (50), and the drain electrode (15) or the source electrode (14) through the transferring through hole (K1,K2), wherein the forming a pixel electrode (50) and a thin film transistor on the base (10) comprises: forming the pixel electrode (50), a gate line (30) and a gate electrode (11) by means of one patterning process; forming a gate insulation layer (12), an active layer (13), a source electrode (14), a drain electrode (15) and a data line (40) by means of one patterning process, forming a conductive channel between the source electrode (14) and the drain electrode (15), characterized in that : the connection electrode (60) comprises a first compensation block (60A) which is a portion of the connection electrode (60) disposed at a side of the connection electrode (60) close to the gate line (30), an orthographic projection of the first compensation block (60A) on the base (10) overlaps at least a portion of an orthographic projection of an edge of the drain electrode (15) or the source electrode (14) at a side adjacent to the gate line (30) on the base (10), and the first compensation block (60A) extends from a main body of the connection electrode (60) towards the gate line (30), and in a plane which is parallel to the substrate, a size of the first compensation block (60A) are smaller than a size of the main body in a direction parallel to a direction of the gate line (30); and the connection electrode (60) comprises a second compensation block (60B) which is another portion of the connection electrode (60) disposed at a side of the connection electrode (60) away from the gate line (30), an orthographic projection of the second compensation block (60B) on the base (10) overlaps at least a portion of an orthographic projection of an edge of the source electrode (14) or the drain electrode (15) at a side away from the gate line (30) on the base (10), the second compensation block (60B) extends from the main body of the connection electrode (60) to a direction away from the gate line (30), in a plane which is parallel to the substrate, a size of the second compensation block (60B) are smaller than a size of the main body in a direction parallel to a direction of the gate line (30), wherein shapes of the first compensation block and/or the second compensation block comprises a rectangle, a trapezoid, a semicircle or a semi-ellipse.
  7. The manufacturing method according to claim 6, wherein the forming a pixel electrode (50), a gate line (30) and a gate electrode (11) by means of one patterning process comprises: depositing a first transparent conductive film and a first metal film on the base (10) sequentially; coating a layer of photoresist on the first metal film, gradient exposing and developing the photoresist using a halftone mask or a gray tone mask, forming an unexposed region at a location where the gate line (30) and the gate electrode (11) to be formed are located, the unexposed region being with a photoresist having a first thickness, forming a partially exposed region at a location where the pixel electrode (50) to be formed is located, the partially exposed region being with a photoresist having a second thickness, forming a fully exposed region at other locations without a photoresist, and the first thickness is greater than the second thickness; etching away the first metal film and the first transparent conductive film in the fully exposed region by means of a first etching process; removing the photoresist in the partially exposed region by means of an ashing process, exposing the first metal film; and etching away the first metal film in the partially exposed region by means of a second etching process, removing a remaining portion of the photoresist and forming the pixel electrode (50), the gate line (30) and the gate electrode (11) on the base (10).
  8. The manufacturing method according to claim 6, wherein the forming a gate insulation layer (12), an active layer (13), a source electrode (14), a drain electrode (15) and a data line (40), forming a conductive channel between the source electrode (14) and the drain electrode (15) by means of one patterning process comprises: depositing a gate insulation film, a semiconductor film and a second metal film (50) on the base (10) on which the pixel electrode (50), the gate line (30) and the gate electrode (11) are formed; coating a layer of photoresist on the second metal film (50), gradient exposing and developing the photoresist using a halftone mask or a gray tone mask, forming an unexposed region at a location where the source electrode (14), the drain electrode (15) and the data line (40) to be formed are located, the unexposed region being with a photoresist having a first thickness, forming a partially exposed region at a location where the conductive channel to be formed is located, the partially exposed region being with a photoresist having a second thickness, forming a fully exposed region at other locations without a photoresist, and the first thickness is greater than the second thickness; etching away the second metal film (50) and the semiconductor film in the fully exposed region by means of a first etching process; removing the photoresist in the partially exposed region by means of an ashing process, exposing the second metal film (50); etching away the second metal film (50) in the partially exposed region by means of a second etching process, removing a remaining portion of the photoresist, forming the gate insulation layer (12), the active layer (13), the source electrode (14), the drain electrode (15) and the data line (40), forming a conductive channel between the source electrode (14) and the drain electrode (15).
  9. The manufacturing method according to claim 6, wherein the forming the passivation layer (16) covering the thin film transistor, and the passivation layer (16) being provided with a transferring through hole (K1,K2) that exposes the pixel electrode (50) and a drain electrode (15) or a source electrode (14) of the thin film transistor simultaneously comprises: depositing a passivation film on a base (10) on which the thin film transistor and the pixel electrode (50) are formed; coating a layer of photoresist on the passivation film, exposing and developing the photoresist using a monotone mask, forming an exposed region at a location of the transferring through hole (K1,K2) without the photoresist, forming an unexposed region at other locations in which the photoresist is remained; etching away the passivation film and the gate insulation layer (12) in the fully exposed region by means of an etching process, forming the passivation layer (16) in which the transferring through hole (K1,K2) is formed and the transferring through hole (K1,K2) exposing a drain electrode (15) and a pixel electrode (50) simultaneously, wherein the transferring through hole (K1, K2) comprises a first through hole portion (K1) and a second through hole portion (K2), the passivation film in the first through hole portion (K1) is etched away and the drain electrode (15) is exposed, and the passivation film and the gate insulation layer (12) in the second through hole portion (K2) are etched away and the pixel electrode (50) is exposed.

Description

TECHNICAL FIELD The present disclosure relates to an array substrate and a manufacturing method thereof, a display panel. BACKGROUND A Liquid Crystal Display (LCD) has characteristics such as small volume, low power consumption, radiationless, and etc., and has developed rapidly in recent years. A mainbody structure of the LCD includes a thin film transistor (TFT) array substrate and a color filter (CF) substrate cell-assembled with each other, liquid crystal (LC) molecules are filled between the array substrate and the color filter substrate and an electric field that drives the deflection of the liquid crystal is formed by controlling a common electrode and a pixel electrode for realizing a gray-scale display. According to the display mode, the LCD may be divided into a twisted nematic (TN) display mode, an in plane switching (IPS) display mode and an advanced super dimension switch (ADS) display mode and the like. The ADS display mode has become a relatively mature display mode, which has advantages of wide view angle, high aperture ratio, high penetration rate, high resolution, fast response speed, low power consumption, and low chromatic aberration and the like. In recent years, on a basis of the ADS display mode, an IADS (Interchange Advanced Super Dimension Switch) display mode is proposed in the prior art. Study indicates that when a dual-gate pixel architecture is used, the IADS display mode can improve luminous efficiency, thereby improving transmittance of a pixel. The dual-gate pixel architecture can reduce the number of source driving integrated circuit ICs and reduce cost. Therefore, the IADS display mode has been increasingly widely used. CN107065347A discloses an array substrate, a liquid crystal display panel and a manufacturing method of the array substrate. The array substrate comprises a substrate, a common electrode, and a pixel electrode, a grid electrode, an active layer, a source/drain electrode, a first auxiliary electrode and a second auxiliary electrode which are positioned between the substrate and the common electrode. The first auxiliary electrode and the pixel electrode are on the same layer, the second auxiliary electrode and the grid electrode are on the same layer, a first insulating layer is arranged between the grid electrode and the active layer, the source/drain electrode is formed on the active layer, and a second insulating layer is arranged between the source/drain electrode and the common electrode. Via holes pass through the first insulating layer and the second insulating layer, a connecting conductor is used for connecting the side face, close to the pixel electrode, of the source/drain electrode, the side face, close to the grid electrode, of the second auxiliary electrode and the pixel electrode through one via hole. The connecting conductor and the common electrode are on the same layer and are insulated from each other. Through the scheme provided by the embodiment of the invention, the quantity of the via holes for connecting the source/drain electrode and the pixel electrode is reduced, and the aperture opening ratio of the pixel can be improved. CN107093584A relates to the technical field of display, and particularly relates to an array substrate, a display panel, a display device and a manufacturing method of the array substrate. The manufacturing method comprises the steps of manufacturing grid lines and pixel electrodes by adopting a first mask plate, manufacturing a thin film transistor and a touch signal line by adopting a second mask plate, manufacturing a first via hole and a second via hole by adopting a third mask plate, and manufacturing a common electrode layer by adopting a fourth mask plate, wherein the common electrode layer comprises a first connecting structure and a common electrode unit, the common electrode unit comprises a second connecting structure, the first connecting structure is contacted with a drain electrode and the pixel electrodes through the first via hole, and the second connecting structure is contacted with the touch signal line through the second via hole. According to the invention, manufacturing of the array substrate is realized through the four mask plates, the number of the mask plates is reduced, and thus the manufacturing cost can be reduced. In the US20160048065A1, a gate line (40) has a two-layered structure comprising a lower gate line (40a) made of material identical to a pixel electrode (70), and positioned in the same layer as the pixel electrode (70), and an upper gate line (40b) layered on the lower gate line (40b), and made of material having a higher electrical conductivity than the transparent conductive material. According to this structure, it is possible to reduce the number of times performing exposure processes in manufacturing an in-plane switching type liquid crystal panel. SUMMARY Embodiments of the present disclosure provides an array substrate and a manufacturing method thereof, a display pane