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EP-4319528-B1 - SEMICONDUCTOR STRUCTURE AS WELL AS MANUFACTURING METHOD THEREFOR, STORAGE CHIP, AND ELECTRONIC DEVICE

EP4319528B1EP 4319528 B1EP4319528 B1EP 4319528B1EP-4319528-B1

Inventors

  • WANG, HONG
  • LI, XIAOJIE

Dates

Publication Date
20260506
Application Date
20220801

Claims (14)

  1. A semiconductor structure, comprising: a substrate (11) on which at least one stacked structure is provided, the stacked structure comprising a plurality of memory cell groups (TCO) arranged in a first direction, each of the memory cell groups (TCO) comprising multiple layers of memory cells (TC) arranged in a second direction; and the first direction is parallel to a surface of the substrate (11), and the second direction is perpendicular to the surface of the substrate (11); the stacked structure further comprises a plurality of horizontal signal lines (3) and a plurality of vertical signal lines (4), wherein the plurality of horizontal signal lines (3) are arranged in the second direction and extend along the first direction, and each of the horizontal signal lines (3) is connected to one layer of memory cells (TC), and the vertical signal lines (4) extend along the second direction and are connected to multiple layers of memory cells (TC) in a same memory cell group (TCO); characterized by a plurality of leading wire posts (5), wherein at least two leading wire posts (5) of the plurality of leading wire posts (5) respectively are in contact with different layers of memory cells (TC) in different memory cell groups (TCO), the at least two leading wire posts utilize the space of different memory cell groups (TCO); and the leading wire posts (5) are electrically connected to the horizontal signal lines (3).
  2. The semiconductor structure according to claim 1, wherein the leading wire posts (5) are arranged along the first direction.
  3. The semiconductor structure according to claim 1, wherein all the memory cells (TC) in a same memory cell group (TCO) are in contact with at most one leading wire post (5) of the plurality of leading wire posts (5).
  4. The semiconductor structure according to claim 1, wherein the number of the plurality of leading wire posts (5) is equal to or greater than the number of layers of the memory cells (TC), and each layer of memory cells (TC) at least comprises one memory cell (TC) in contact with a corresponding leading wire post (5).
  5. The semiconductor structure according to claim 1, wherein the number of leading wire posts (5) in contact with one of the memory cell groups (TCO) is less than the number of layers of the memory cells (TC) in the one memory cell group (TCO).
  6. The semiconductor structure according to claim 1, wherein each of the memory cells (TC) comprises a channel region (22) and a source/drain doped region (21) arranged in a third direction, the source/drain doped region (21) is arranged at two sides of the channel region (22), and the third direction is parallel to the surface of the substrate (11).
  7. The semiconductor structure according to claim 6, wherein each of the plurality of horizontal signal lines (3) is a bit line, and each of the plurality of vertical signal lines (4) is a word line, the bit line is connected to the source/drain doped region (21), and the word line is connected to the channel region (22); and at least one of the plurality of leading wire posts (5) penetrates through the source/drain doped region (21) in at least one of the memory cells (TC), wherein the source/drain doped region (21) comprise a first source/drain doped region (211) and a second source/drain doped region (212), the first source/drain doped region (211) is located between the bit line and the channel region (22), and the second source/drain doped region (212) is located at a side of the channel region (22) opposite to the first source/drain doped region (211); and the leading wire post (5) penetrates through the first source/drain doped region (211).
  8. The semiconductor structure according to claim 6, wherein each of the plurality of horizontal signal lines (3) is a word line, and each of the plurality of vertical signal lines (4) is a bit line, the bit line is connected to the source/drain doped region (21), and the word line is connected to the channel region (22); and at least one of the plurality of leading wire posts (5) penetrates through the channel region (22) in at least one of the memory cells (TC).
  9. The semiconductor structure according to claim 6, wherein the memory cell (TC) further comprises a bit line contact area (23), the bit line contact area (23) connecting the bit line to the source/drain doped region (21), wherein at least one of the plurality of leading wire posts (5) penetrates through the bit line contact area (23) in one of the memory cells (TC).
  10. The semiconductor structure according to claim 9, wherein the numbers of memory cells (TC) which the at least two leading wire posts (5) penetrate through are different from each other.
  11. The semiconductor structure according to claim 1, wherein two adjacent leading wire posts (5) of the plurality of leading wire posts (5) are at least spaced by one of the plurality of memory cell groups (TCO), wherein the number of memory cells (TC) between the two adjacent leading wire posts (5) is fixed, or, the area of a directly facing region between the two adjacent leading wire posts (5) is directly proportional to the number of memory cell groups (TCO) between the two adjacent leading wire posts (5).
  12. The semiconductor structure according to claim 1, wherein the number of stacked structures is greater than one, the plurality of horizontal signal lines (3) of a same stacked structure comprises a first horizontal signal line to N-th horizontal signal line successively arranged in the second direction, N being a positive integer greater than 1; and two stacked structures of the stacked structures further comprise a plurality of wires (7), each wire (7) connects two leading wire posts (5), which are in contact with different stacked structures of the stacked structures, of the plurality of leading wire posts (5), and a sum of sequence numbers of the two horizontal signal lines (3) electrically connected to the two leading wire posts (5) being N+1.
  13. The semiconductor structure according to claim 1, wherein the at least two leading wire posts (5) of the plurality of leading wire posts (5) are in contact with different memory cells (TC) in a same memory cell group (TCO).
  14. A method for manufacturing a semiconductor structure, comprising: providing a substrate, forming at least one stacked structure on the substrate, the stacked structure comprising a plurality of memory cell groups arranged in a first direction, each of the memory cell groups comprising multiple layers of memory cells arranged in a second direction; and the first direction is parallel to a surface of the substrate (11), and the second direction is perpendicular to the surface of the substrate (11); the stacked structure further comprises a plurality of horizontal signal lines (3) and a plurality of vertical signal lines (4), wherein the plurality of horizontal signal lines (3) are arranged in the second direction and extend along the first direction, and each of the horizontal signal lines (3) is connected to one layer of memory cells (TC), and the vertical signal lines (4) extend along the second direction and are connected to multiple layers of memory cells (TC) in a same memory cell group (TCO); characterized by a plurality of leading wire posts (5), wherein at least two leading wire posts (5) of the plurality of leading wire posts (5) respectively are in contact with different layers of memory cells (TC) in different memory cell groups (TCO), the at least two leading wire posts utilize the space of different memory cell groups (TCO); and the leading wire posts (5) are electrically connected to the horizontal signal lines (3).

Description

CROSS-REFERENCE TO RELATED APPLICATION The present application claims priority to Chinese Patent Application No. 202210723121.3, filed on June 21, 2022 and entitled "SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME, MEMORY CHIP AND ELECTRONIC DEVICE". TECHNICAL FIELD The embodiments of the disclosure belong to the field of semiconductors and particularly relate to a semiconductor structure and a method for manufacturing the semiconductor structure, a memory chip and an electronic device. BACKGROUND A semiconductor structure includes a plurality of memory cells, and the memory cells are connected to a peripheral circuit to execute a storage function. With an improvement of an integration level of the semiconductor structure, the number of the memory cells capable of being accommodated in the semiconductor structure increases and the performance of the semiconductor structure gets better. However, many spaces in the current semiconductor structure are wasted. Besides, under the limit of factors of physical properties, the volume of the memory cell has reached a scaling limit. Under the limit of process factors, it is also difficult to increase the number of stacked layers of the memory cell. Background may be found in US 2022/130831 A1 (LEE SI-WOO [US] ET AL) 28 April 2022 and US 2019/164985 A1 (LEE KISEOK [KR] ET AL) 30 May 2019. Therefore, it is urgent to provide a semiconductor structure in a new architecture, so as to improve the integration level of the semiconductor structure. SUMMARY The present invention is defined in appended independent claims 1 and 14 to which reference should be made. Advantageous features are set out in the appended dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments conforming to the disclosure and, together with the description, serve to explain the principles of the disclosure. It is apparent that the accompanying drawings described below merely show some embodiments of the disclosure, and those of ordinary skill in the art can further obtain other drawings according to those accompanying drawings without making creative efforts. FIG. 1 illustrates a top view of a semiconductor structure.FIG. 2 illustrates an enlarged partial view of FIG. 1.FIG. 3 illustrates a sectional view along a direction A-A1 of FIG. 2.FIG. 4 illustrates a schematic diagram of a stacked structure provided by an embodiment of the disclosure.FIG. 5 to FIG. 11 respectively illustrate partial plan views of seven different semiconductor structures provided by the embodiments of the disclosure.FIG. 12 illustrates a schematic diagram of a memory cell group provided by an embodiment of the disclosure.FIG. 13 illustrates a schematic partial side view of a semiconductor structure provided by an embodiment of the disclosure.FIG. 14 illustrates a schematic diagram of another memory cell group provided by an embodiment of the disclosure.FIG. 15 illustrates a schematic partial side view of another memory cell group provided by the embodiment of the disclosure.FIG. 16 illustrates a schematic diagram of another memory cell group provided by an embodiment of the disclosure.FIG. 17 illustrates a schematic partial side view of another semiconductor structure provided by an embodiment of the disclosure.FIG. 18 to FIG. 21 respectively illustrate schematic diagrams of four memory cell groups provided by the embodiments of the disclosure.FIG. 22 shows a schematic diagram of a structure module provided by an embodiment of the disclosure.FIG. 23 to FIG. 31 illustrate schematic structural diagrams corresponding to stairs in a method for manufacturing a semiconductor structure provided by the embodiments of the disclosure.FIG. 32 to FIG. 35 illustrate schematic structural diagrams corresponding to stairs in another method for manufacturing a semiconductor structure provided by the embodiments of the disclosure.FIG. 36 illustrates a schematic diagram of another memory cell group provided by an embodiment of the disclosure.FIG. 37 to FIG. 38 respectively illustrate partial top views of two different semiconductor structures provided by the embodiments of the disclosure. DETAILED DESCRIPTION FIG. 1 is a top view of a semiconductor structure. FIG. 2 is an enlarged view of a stair in a dotted line circle in FIG. 1. FIG. 3 is a sectional view along a direction A-A1 in FIG. 2. Referring to FIG. 1 to FIG. 3, the semiconductor structure includes a memory cell area 100 and a staircase 200. Multiple layers of memory cells are provided in the memory cell area 100. Multiple stairs are arranged in the staircase 200, and the stairs and the multiple layers of memory cells are arranged in one-to-one correspondences. A connecting layer (not shown FIG. 1 to FIG. 3) can be arranged in the stair, a leading wire post 300 can be arranged on the stair, and the leading wire post 300 is electrically connected to the memory cell