EP-4327274-B1 - SEGMENTATION OF CROSS SECTIONS OF HIGH ASPECT RATIO STRUCTURES

Inventors

• Klochkov, Dmitry
• NEUMANN, JENS TIMO
• KORB, THOMAS
• Töppe, Eno
• PERSCH, JOHANNES
• SRIKANTHA, Abhilash
• Freytag, Alexander

Dates

Publication Date

20260506

Application Date

20220323

Claims (15)

1. A computer-implemented method of training a machine-learning logic for segmentation of rings of pillar cross sections in high aspect ratio, HAR, structures, the method comprising: providing cross section images of a plurality of pillars, binary annotating rings in the cross section images with two alternating labels, training a first machine learning logic based on the binary annotated rings, segmenting the cross section images or further cross section image with the trained first machine-learning logic to provide binary segmented images, multi-level annotating segmented rings in the binary segmented images to provide multi-level annotated images, and training a second machine learning logic as the machine-learning logic for segmentation of rings based on the multi-level annotated images.
2. The method of claim 1, wherein the first machine learning logic includes a random forest model.
3. The method of claim 1 or 2, wherein the second machine learning logic includes a neural network.
4. The method of any one of claims 1 to 3, further comprising re-training the first machine learning logic based on corrected binary segmented images.
5. The method of any one of claims 1 to 4, wherein training the second machine learning logic is based on a first part of the multi-level annotated images, and wherein the method further comprises testing the trained second machine learning logic based on a second part of the multi-level annotated images different from the first part.
6. A computer-implemented method of analyzing rings of pillar cross sections in high aspect ratio, HAR structures, the method comprising: providing a cross-section image of a pillar, segmenting rings in the cross-section using a trained machine learning logic, and determining parameters of the rings based on the segmented rings. wherein the machine-learning logic is the second machine-learning logic trained with the method of any one of claims 1 to 5.
7. The method of claim 6, further comprising identifying contours of the rings based on the segmented rings, wherein determining the parameters is based on the identified contours.
8. The method of claims 6 or 7, wherein the parameters include parameters selected from the group consisting of ring radii and ring diameters.
9. The method of any one of claims 6 to 8, further comprising identifying deviations of the parameters from nominal or intended values.
10. The method of any one of claims 6 to 9, further comprising: obtaining a 3D tomographic image of a semiconductor sample, selecting a subset of 2D cross section image segments including the cross-section image of the pillar from the 3D tomographic image, each comprising cross section images of a set of HAR structures, identification of a contour of each HAR structure within the set of HAR structures in the subset of 2D cross section images, extraction of deviation parameters from the contours of the HAR structures of the set of HAR structures, analyzing the deviation parameters, wherein the deviation parameters comprise one or more of a displacement from an ideal position, a deviation in radius or diameter, a deviation from a cross section area, a deviation from a shape of a cross section.
11. The method according to claim 10, wherein the step of analyzing the deviation parameters comprises performing statistical analysis of at least one deviation parameter of at least one HAR structure of the set of HAR structures.
12. A semiconductor inspection device, comprising: a focused ion beam device, FIB, adapted for milling of a series of cross sections of an integrated semiconductor sample, a scanning electron beam microscope, SEM, adapted for imaging of the series of cross sections of the integrated semiconductor sample, a controller for operating a set of instructions, adapted for performing the method steps of any one of claims 6 to 10.
13. The semiconductor inspection device of claim 12, wherein the focused ion beam, FIB, and the electron beam microscope, SEM, form an angle of about 90° with one another.
14. The semiconductor inspection device of claim 12 or 13, further comprising a Laser beam device for cutting the integrated semiconductor sample from a wafer.
15. A computer program, including instructions, which, when executed on a processor, cause execution of the method of any one of claims 1 to 11.

Description

Field of the invention The present invention relates to a three-dimensional circuit pattern inspection and measurement technique by cross sectioning of integrated circuits. More particularly, the present invention relates to a method of obtaining a 3D volume image of a channel or high aspect ratio (HAR) structure within an integrated semiconductor sample and to a corresponding computer program product and a corresponding semiconductor inspection device. The method, computer program product and device can be utilized for quantitative metrology, defect detection, defect review, and inspection of shape or cross section, inclination or trajectory of a channel or HAR structure within an integrated semiconductor sample by using a scanning charged particle microscope. Background of the invention Semiconductor structures are amongst the finest man-made structures and suffer from very few imperfections only. These rare imperfections are the signatures which defect detection or defect review or quantitative metrology devices are looking for. Fabricated semiconductor structures are based on prior knowledge. For example, in a logic type sample, metal lines are running parallel in metal layers or high aspect ratio (HAR) structures or metal vias run perpendicular to the metal layers. The angle between metal lines in different layers is either 0° or 90°. On the other hand, for VNAND type structures it is known that their cross sections are spherical on average. Integrated Semiconductors are fabricated by processing a series of layers on a Silicon Substrate by planar integration techniques. Each layer is first planarized and then structured by a pattern within a lithography process by a projection exposure apparatus. The lithography pattern is transferred into the silicon layer by several techniques, including etching, deposition, doping or implantation. A cross section perpendicular to a set of layers is shown in Figure 1. The integrated semiconductor 50 comprises a set of layers 54.1, 54.2, ... 54.22, which are fabricated by planar integration techniques parallel to the top surface 52, which extends in x-y-direction. Beyond the lowest layer 54.22 is the bulk Silicon substrate 51 of the semiconductor substrate or wafer, which is not shown in its entire depth. The lowest layer 54.22 is a layer in which doped structures 58 in the Silicon substrate are formed by e.g. implantation. On top of this layer, a series of so-called metal layers structured with metal conductors, such as metal layers 54.1, 54.3, ...54.17... alternates with a series of isolation layers, such as isolation layers 54.2, 54.4, .... The isolation layers comprise interconnects to contact two neighboring metal layers, such as vias 55 between a metal structure 56 in metal layer 54.1 and the metal structure in metal layer 54.3. The lowest metal layer comprises a series of gates 57 with contacts 59 in the adjacent isolation layer. With increasing depth in z-direction, the minimum feature sizes in the layers become smaller. The current minimum feature size or critical dimension in the lowest, most critical layers is actually below 10nm, for example 7nm or 5nm, and approaching below 3 nm in near future. With the small extension of the minimum feature sizes, the requirement on the lateral placement of the layers in x- and y-direction becomes more and more demanding. The lateral overlay accuracy of two layers typically is in the order of 1/3 of the minimum feature size in the two layers. Thus, the lateral alignment of the lowest layers must be in the order of few nm, and in near future even below 1 nm. Figure 2 shows another example of a cross section through a semiconductor device, such as a NAND memory device. In this example, several pillars, such as the three pillars indicated by reference number 60, extend through a large set of metal and isolation layers 54.1, ... 54.k, ... 54.z, and establish conducting connections perpendicular to the layers. The pillars 60 are also called HAR (high aspect ratio)-structures, or sometimes contact channels. While metal structures within the metal layers, parallel to the surface 52 are fabricated at once with the high precision of planar fabrication techniques, the pillars 60 are formed by a large series or small metal structures in each subsequent layer, stacked on top of each other. The pillars thus can suffer from several damages, thus as errors in the processing of individual planar layers as well as overlay errors between subsequent planar layers. Errors or defects within the pillars, however, limit the performance of a semiconductor device or may cause failure of such a device. One kind of pillars are so-called memory channels in 3D memory chips. Prior art techniques employed to analyze integrated semiconductor devices are currently utilizing a 2D imaging approach. For example, a thin slice or lamella is formed from the semiconductor device, e.g. by ion beam milling, and the thin sample is extracted by a probe. The lamell