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EP-4345619-B1 - PROCESSOR, PHYSICAL REGISTER MANAGEMENT METHOD, AND ELECTRONIC APPARATUS

EP4345619B1EP 4345619 B1EP4345619 B1EP 4345619B1EP-4345619-B1

Inventors

  • Yu, Yaxuan

Dates

Publication Date
20260506
Application Date
20220517

Claims (7)

  1. A processor (10), comprising: a plurality of physical registers, configured to be multiplexed by a plurality of threads (13) executed on the processor, wherein the plurality of physical registers are shared by the plurality of threads (13); a thread information storage apparatus (12), configured to record a corresponding relationship between the plurality of physical registers and the plurality of threads (13); and a controller (24), configured to modify the corresponding relationship in the thread information storage apparatus (12) in response to one of the plurality of physical registers being allocated to one of the plurality of threads and/or one of the plurality of physical registers being released; the controller (24) is further configured to, record a first thread number of a first thread among the plurality of threads (13) in an item corresponding to a first selected physical register among the plurality of physical registers in the thread information storage apparatus (12) in response to the first selected physical register being allocated to the first thread and the first thread setting the first selected physical register to invalid, wherein the first selected physical register being set to invalid indicates that data in the first selected physical register is unavailable; characterized in that the controller (24) is further configured to: in response to a broadcasting operation for the first selected physical register, acquire a second thread number of a second thread that initiates the broadcasting operation among the plurality of threads (13), and acquire the first thread number recorded in the item corresponding to the first selected physical register in the thread information storage apparatus (12); determine the broadcasting operation as a valid broadcasting operation in response to the second thread number being identical to the first thread number; and determine the broadcasting operation as an invalid broadcasting operation in response to the second thread number being different from the first thread number; wherein the broadcasting operation for the first selected physical register indicates that a thread that generates data has prepared the data and stored the data in the first selected physical register.
  2. The processor according to claim 1, wherein the controller (24) is further configured to record the invalid broadcasting operation and the second thread number of the second thread that initiates the invalid broadcasting operation.
  3. The processor according to claim 2, wherein the controller (24) is further configured to prevent the second thread from writing data into the first selected physical register in response to determining that the broadcasting operation is the invalid broadcasting operation and determining the second thread number.
  4. A physical register management method, comprising: (S300) enabling a plurality of physical registers to be multiplexed by a plurality of threads executed on a processor, wherein the plurality of physical registers are shared by the plurality of threads; (S310) recording a corresponding relationship between the plurality of physical registers and the plurality of threads by using a thread information storage apparatus; and modifying the corresponding relationship in the thread information storage apparatus in response to one of the plurality of physical registers being allocated to one of the plurality of threads and/or one of the plurality of physical registers being released; recording a thread number of a first thread among the plurality of threads in an item corresponding to a first selected physical register among the plurality of physical registers in the thread information storage apparatus in response to the first selected physical register being allocated to the first thread and the first thread setting the first selected physical register to invalid, wherein the first selected physical register being set to invalid indicates that data in the first selected physical register is unavailable; characterized by : in response to the broadcasting operation for the first selected physical register, acquiring a second thread number of a thread that initiates the broadcasting operation among the plurality of threads, and acquiring the first thread number recorded in the item corresponding to the first selected physical register in the thread information storage apparatus; determining the broadcasting operation as a valid broadcasting operation in response to the second thread number being identical to as the first thread number; and determining the broadcasting operation as an invalid broadcasting operation in response to the second thread number being different from the first thread number; wherein the broadcasting operation for the first selected physical register indicates that a thread that generates data has prepared the data and stored the data in the first selected physical register.
  5. The method according to claim 4, further comprising: recording the invalid broadcasting operation and the second thread number of the second thread that initiates the invalid broadcasting operation.
  6. The method according to claim 5, further comprising: preventing the second thread from writing data into the first selected physical register in response to determining that the broadcasting operation is the invalid broadcasting operation and determining the second thread number.
  7. An electronic device (40), comprising the processor (41) according to any one of claims 1 to 3.

Description

This application claims the priority of Chinese Patent Application No.202111031336.0 filed on September 3, 2021. TECHNICAL FIELD Embodiments of the present disclosure relate to a processor, a physical register management method, and an electronic apparatus. BACKGROUND CPU (Central Processing Unit) multithreading is called SMT (Simultaneous multithreading). Multithreading can make multiple threads on the same processor execute synchronously and share the resources of the processor by copying a structural state on the processor. In order to realize an out-of-order execution of the processor, a physical register is usually renamed to map a logical register in the instruction to the physical register. When the physical registers in the current processor are multiplexed by multiple threads, it is easy to make mistakes. For example, after a thread A releases a physical register prn1, the physical register prn1 is reallocated to a thread B. If the thread A broadcasts a physical register number of the prn1 due to, for example, a hardware error after the thread A releases the physical register prn1, the thread B will think that the data of the physical register prn1 is ready, but in fact the data of the physical register prn1 is not ready at this time, resulting in an error. Faced with this kind of error, the conventional thinking is that a processor hardware recognizes that the thread A has the physical register prn1 and prevents the thread A from broadcasting its physical register number. However, in practical application or actual circuit design, it is not only difficult to realize the above ideas by using the processor hardware, but also easy to make mistakes. For example, the newly allocated instruction selects the same physical register at the same time, or the newly allocated instruction is issued in advance before it is issued by its producer. US 9 817 664 B2 discloses a register caching techniques for thread switches. US 2014/244977 A1 discloses a deferred saving of registers in a shared register pool for a multithreaded microprocessor. US 2014/122842 A1 discloses an efficient usage of a register file mapper mapping structure. SUMMARY It is an object of the present invention to provide a processor, a physical register management method, and an electronic apparatus. The object is achieved by the features of the respective independent claims. Further embodiments are defined in the corresponding dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS In order to more clearly explain the technical scheme of the embodiments of the present disclosure, the following drawings will be briefly introduced. Obviously, the drawings described below only relate to some embodiments of the present disclosure, and are not limited to the present disclosure. FIG. 1 is a block diagram of a processor provided by at least one embodiment of the present disclosure;FIG. 2 is a block diagram of a processor provided by at least one embodiment of the present disclosure;FIG. 3 is a flowchart of a physical register management method provided by at least one embodiment of the present disclosure; andFIG. 4 is a block diagram of an electronic device provided by at least one embodiment of the present disclosure. DETAILED DESCRIPTION In order to make the purpose, technical scheme and advantages of the embodiment of the disclosure more clearly, the technical scheme of the embodiment of the present disclosure will be described clearly and completely with the attached drawings. Obviously, the described embodiment is a part of the embodiment of the present disclosure, not the whole embodiment. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary people in the field without creative labor belong to the scope of protection of the present disclosure. Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have their ordinary meanings as understood by people with ordinary skills in the field to which the present disclosure belongs. The terms "first", "second" and the like used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "a", "an" or "the" do not indicate a quantity limit, but indicate the existence of at least one. Similar words such as "comprising" or "including" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connected" or "connected" are not limited to physical or mechanical connection, but can comprise electrical connection, whether direct or indirect. "Up", "Down", "Left" and "Right" are only used to indicate the relative positional relationship. When the absolute position of the described object changes, the relative positional relationship may also change accordingly. At least one em