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EP-4348949-B1 - METHOD AND DEVICE FOR TIMING RECOVERY DECOUPLED FEE ADAPTATION IN SERDES RECEIVERS

EP4348949B1EP 4348949 B1EP4348949 B1EP 4348949B1EP-4348949-B1

Inventors

  • ALNABULSI, BASEL

Dates

Publication Date
20260513
Application Date
20220526

Claims (15)

  1. A receiver circuit (300) comprising: a plurality of feed-forward equalizers (350) configured to recover data from a received signal, each of the plurality of feed-forward equalizers configured to perform feed-forward adaptation including adjusting in phase at least one of a precursor tap and a postcursor tap to determine a phase location at which to sample a characteristic eye of the received signal, and to provide a metric for the phase location, the metric indicating signal quality when sampling at the phase location; a processor (360) configured to selectively enable feed-forward adaptation of one or more of the plurality of feed-forward equalizers (350); and a timing recovery circuit (370) configured to selectively prevent use of contributions from the plurality of feed-forward equalizers (350) for which feed-forward adaptation is enabled, to selectively permit use of contributions from the plurality of feed-forward equalizers (350) for which feed-forward adaptation is disabled, and to perform timing recovery including adjusting phase of a clock (380) based on contributions received from the plurality of feed-forward equalizers (350) for which feed-forward adaptation is disabled, the received contributions including the recovered data and the metrics from the plurality of feed- forward equalizers (350) for which feed-forward adaptation is disabled.
  2. The receiver circuit (300) of claim 1, wherein the timing recovery circuit (370) is configured to store an interleave specific vector including a plurality of indexes, the plurality of indexes indicating whether use of a contribution from a respective one of the plurality of feed forward equalizers (350) is enabled, and based on the plurality indexes, to use contributions from the plurality of feed-forward equalizers (350) for which feed-forward adaptation is disabled.
  3. The receiver circuit (300) of claim 1 or 2, wherein the plurality of feed-forward equalizers (350) is configured to provide respectively a plurality of interleave sampling slices of the received signal and are further configured to perform an iterative adaptation process on the plurality of interleave sampling slices of the received signal to provide the recovered data; and/or wherein the iterative adaptation process includes iteratively cycling through the plurality of interleave sampling slices and, during each stage of a cycle through the plurality of interleave sampling slices, enabling feed-forward adaptation for a respective one of the plurality of interleave sampling slices and disabling feed forward adaptation for the other ones of the plurality of interleave sampling slices.
  4. The receiver circuit (300) of one of claims 1 to 3, wherein: the processor (360) is configured to enable feed-forward adaptation of one of the plurality of feed-forward equalizers (350) while disabling feed-forward adaptation of other ones of the plurality of feed-forward equalizers (350); and the timing recovery circuit (370) is configured to permit use of a contribution from the one of the plurality of feed-forward equalizers (350) for which feed-forward adaptation is disabled and prevent use of contributions from the other ones of the plurality of feed-forward equalizers(350).
  5. The receiver circuit (300) of one of claims 1 to 4, wherein: the processor (360) is configured to iteratively cycle through the plurality of feed forward equalizers(350), where each iteration includes one of the plurality of feed-forward equalizers (350) performing feed-forward adaptation and not providing a contribution to the timing recovery; and the timing recovery circuit (370) is configured to, during each of the iterations, prevent use of a contribution from the one of the plurality of feed-forward equalizers (350) performing feed forward adaptation; and/or wherein: the processor (360) is configured to, during each of the iterations, disable feed-forward adaptation of the plurality of feed-forward equalizers (350) other than the one of the plurality of feed forward equalizers (350) performing feed-forward adaptation; and the timing recovery circuit (370) is configured to, during each of the iterations, permit use of contributions from other ones of the plurality of feed-forward equalizers (350) for which feed forward adaptation is disabled.
  6. The receiver circuit (300) of one of claims 1 to 5, wherein each of the plurality of feed forward equalizers (350) is configured to perform feed-forward adaptation when enabled based on a signal -to-noise ratio of corresponding samples of the received signal.
  7. The receiver circuit (300) of one of claims 1 to 6, wherein each of the plurality of feed forward equalizers (350) is configured to, during feed-forward adaptation, sweep the phase of the at least one of the precursor tap and the postcursor tap over a plurality of phases, to measure a metric at each of the plurality of phases, and sample the characteristic eye of the received signal at the phase of the one of the plurality of phases providing a better metric than the metrics of other ones of the plurality of phases.
  8. The receiver circuit (300) of one of claims 1 to 7, further comprising: an analog front-end device configured to receive and amplify an input signal to provide the received signal; and an interleaving interface configured to, based on the phase of the clock, direct the received signal to each of the plurality of feed-forward equalizers (350); and/or wherein the analog front-end device comprises a continuous time linear equalizer configured to boost a predetermined range of frequencies of the input signal based on a frequency boost profile, wherein the frequency boost profile is indicative of a ranging in an amount of frequency boost over time including a zero location and an amount of peaking.
  9. A method of operating a receiver device (300), the method comprising: receiving a signal at a plurality of feed-forward equalizers (350) and recovering data using the plurality of feed-forward equalizers (350); selectively enable feed-forward adaptation of one or more of the plurality of feed forward equalizers (350); at the one or more of the plurality of feed-forward equalizers (350), performing feed forward adaptation including adjusting in phase at least one of a precursor tap and a postcursor tap to determine a phase location at which to sample a characteristic eye of the received signal and providing a metric for the phase location, the metric indicating signal quality when sampling at the phase location; selectively preventing use of contributions from the plurality of feed-forward equalizers (350) for which feed-forward adaptation is enabled; selectively permitting use of contributions from the plurality of feed-forward equalizers (350) for which feed-forward adaptation is disabled; and performing timing recovery including adjusting phase of a clock based on contributions received from the plurality of feed-forward equalizers (350) for which feed-forward adaptation is disabled, the received contributions including the recovered data and the metrics from the plurality of feed-forward equalizers (350) for which feed-forward adaptation is disabled.
  10. The method of claim 9, further comprising: storing an interleave specific vector including a plurality of indexes, the plurality of indexes indicating whether use of a contribution from a respective one of the plurality of feed forward equalizers (350) is enabled; and based on the plurality indexes, using contributions from the plurality of feed forward equalizers (350) for which feed-forward adaptation is disabled for timing recovery.
  11. The method of claim 9 or 10, wherein performing at the plurality of feed forward equalizers (350) an iterative adaptation process on the received signal to provide the recovered data, wherein a plurality of interleave sampling slices of the received signal are sampled respectively by the plurality of feed-forward equalizers (350), or further comprising: enabling feed-forward adaptation of one of the plurality of feed-forward equalizers (350) while disabling feed-forward adaptation of other ones of the plurality of feed-forward equalizers (350); and permitting use of a contribution from the one of the plurality of feed-forward equalizers (350) for which feed-forward adaptation is disabled and prevent use of contributions from the other ones of the plurality of feed-forward equalizers (350).
  12. The method of one of claims 9 to 11, further comprising: iteratively cycling through the plurality of feed-forward equalizers (350), where each iteration includes at one of the plurality of feed-forward equalizers (350) performing feed-forward adaptation and not providing a contribution to the timing recovery from the one of the plurality of feed-forward equalizers (350); and during each of the iterations, preventing use of a contribution from the one of the plurality of feed-forward equalizers (350) performing feed-forward adaptation; and/or wherein the iteratively cycling through the plurality of feed-forward equalizers (350) comprises performing a plurality of iterations, where each iteration includes permitting a respective one of the plurality of feed-forward equalizers (350) for that cycle to perform feed-forward adaptation and disabling other ones of the plurality of feed-forward equalizers (350).
  13. The method of claim 12, wherein: during each of the iterations, disabling feed-forward adaptation of the plurality of feed-forward equalizers (350) other than the one of the plurality of feed-forward equalizers (350) performing feed-forward adaptation; and during each of the iterations, permitting use of contributions from other ones of the plurality of feed-forward equalizers (350) for which feed-forward adaptation is disabled.
  14. The method of one of claims 9 to 13, further comprising at each of the plurality of feed forward equalizers (350) performing feed-forward adaptation when enabled based on a signal-to-noise ratio of corresponding samples of the received signal.
  15. The method of one of claims 9 to 14, further comprising at each of the plurality of feed forward equalizers (350) for which feed-forward adaptation is enabled, sweeping the phase of the at least one of the precursor tap and the postcursor tap over a plurality of phases, measuring a metric at each of the plurality of phases, and sampling the characteristic eye of the received signal at the phase of the one of the plurality of phases providing a better metric than the metrics of other ones of the plurality of phases, or further comprising: receiving and amplifying an input signal to provide the received signal; and based on the phase of the clock, direct the received signal to each of the plurality of feed-forward equalizers (350); or further comprising boosting a predetermined range of frequencies of the input signal based on a frequency boost profile, wherein the frequency boost profile is indicative of a ranging in an amount of frequency boost over time including a zero location and an amount of peaking.

Description

CROSS-REFERENCES TO RELATED APPLICATIONS This application is a PCT International Application of United States Patent Application 17/334,281 filed on May 28, 2021. BACKGROUND OF THE INVENTION The present invention generally relates to communication systems and integrated circuit (IC) devices. More specifically, the present invention provides for a method and device for timing recovery decoupled feed-forward equalizer (FFE) adaptation in serializer/deserializer (SerDes) receiver device. Over the last few decades, the use of communication networks has exploded. In the early days of the Internet, popular applications were limited to emails, bulletin boards, and mostly informational and text-based web page surfing. The amount of data transferred by such applications was relatively small. Today, the Internet and mobile applications demand a huge amount of bandwidth for transferring photo, video, music, and other multimedia files. For example, a social networking platform can process more than 500TB of data daily. With such high demands on data storage and data transfer, existing data communication systems need to be improved to address these needs. With the rapidly rising demand for greater operational speed and data throughput, an important aspect of signal processing to address is signal equalization at the receiver, which is the process of removing distortions incurred by a signal being transmitted through a channel. Such signal integrity impairments can be addressed using signal equalization techniques such as feed-forward equalization (FFE), decision-feedback equalization (DFE), continuous-time linear equalization (CTLE), and the like and combinations thereof. There have been many conventional types of methods and devices for signal equalization. Unfortunately, such conventional methods and devices suffer from various drawbacks and limitations, including those related to performance, size, cost, etc. Therefore, improved communication systems with devices and methods using more efficient signal equalization are highly desired. US 2002/080898 A1 discloses a multi-path parallel receiver in which an analog-to-digital converter ("ADC") and a digital signal processor ("DSP") are implemented with parallel paths that operate at lower rates than the received data signal. The parallel DSP-based receiver includes a separate timing recovery loop for each ADC path. The separate timing recovery loops can be used to compensate for timing phase errors in the clock generation circuit that are different for each path. US 2021/610107 A1 discloses a multi-tap Differential Feedforward Equalizer (DFFE) configuration with both precursor and postcursor taps. The DFFE has reduced noise and/or crosstalk characteristics when compared to a Feedforward Equalizer (FFE) since DFFE uses decision outputs of slicers as inputs to a finite impulse response (FIR) unlike FFE which uses actual analog signal inputs. The digital outputs of the tentative decision slicers are multiplied with tap coefficients to reduce noise. Further, since digital outputs are used as the multiplier inputs, the multipliers effectively work as adders which are less complex to implement. The decisions at the outputs of the tentative decision slicers are tentative and are used in a FIR filter to equalize the signal; the equalized signal may be provided as input to the next stage slicers. BRIEF SUMMARY OF THE INVENTION It is the object of the present invention to provide an improved receiver device and a method of operating same. This object is solved by the subject matter of the independent claims which define the present invention. Preferred embodiments of the present invention are defined by the dependent claims. The present invention generally relates to communication systems and integrated circuit (IC) devices. More specifically, the present invention provides for a method and device for timing recovery decoupled feed-forward equalizer (FFE) adaptation in a serializer/deserializer (SerDes) receiver device. Merely by way of example, the present invention is applied to communication systems using pulse-amplitude modulation (PAM). However, the present invention has a much broader range of applicability, such as other Ethernet systems, optical systems, and the like. According to an example, the present invention provides a communication system and a receiver device configured to perform FFE adaptation process decoupled from a timing recovery loop of the device. The receiver device can include an analog front-end (AFE) device, which is coupled to a time-interleaved (TI) interface. The TI interface is coupled in a timing recovery feedback loop to FFE equalizers, a digital signal processor (DSP), a delay timing loop (DTL) device, and a clock device. The clock device feeds back to the TI interface to complete the timing recovery loop. The DSP has an additional pathway to the FFE equalizers, which has an additional pathway to the DTL device. In a specific example, the DTL loo