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EP-4374225-B1 - DEFECTIVITY QUANTIFIER DETERMINATIONS FOR LITHOGRAPHICAL CIRCUIT FABRICATION PROCESSES THROUGH OFF-TARGET PROCESS PARAMETERS

EP4374225B1EP 4374225 B1EP4374225 B1EP 4374225B1EP-4374225-B1

Inventors

  • LATYPOV, AZAT
  • KIM, YOUNG CHANG
  • FENGER, GERMAIN LOUIS

Dates

Publication Date
20260506
Application Date
20210824

Claims (15)

  1. A method comprising: by a computing system (100, 500): determining (402) a defectivity quantifier (310) for a lithographical circuit fabrication process performed with a target value (210) for a process parameter of the lithographical circuit fabrication process, wherein the defectivity quantifier (250, 310) specifies a quantitative value for a stochastic effect on the lithographical circuit fabrication process, and wherein determining the defectivity quantifier (310) comprises: modifying (404) the target value (210) for the process parameter to obtain an off-target value (220) for the process parameter; determining (406) a defectivity quantifier (250) for the lithographical circuit fabrication process performed with the off-target value (220) for the process parameter; and determining the defectivity quantifier (310) for the lithographical circuit fabrication process performed with the target value (210) for the process parameter by extrapolating (408) from the determined defectivity quantifier (250) for the lithographical circuit fabrication process performed with the off-target value (220) for the process parameter; and providing (410) the determined defectivity quantifier (310) for the lithographical circuit fabrication process performed with the target value (210) for the process parameter for assessment of the lithographical circuit fabrication process.
  2. The method of claim 1, wherein the stochastic effect comprises a particular stochastic-induced defect in circuits manufactured via the lithographical circuit fabrication process with the target value (210) for the process parameter and wherein the defectivity quantifier (250, 310) comprises a defect probability for the particular stochastic-induced defect.
  3. The method of claim 1 or 2, comprising determining the defectivity quantifier (250) for the lithographical circuit fabrication process performed with the off-target value (220) for the process parameter through stochastic simulations, experimental measurements, or a combination of both.
  4. The method of any of claims 1-3, wherein modifying the target value (210) for the process parameter comprises adjusting a dose value, a focus value, a photoresist parameter values, a photomask dimension value of exposed features, or any combination thereof.
  5. The method of any of claims 1-4, wherein extrapolating comprises applying a logarithmic curve-fitting extrapolation process using, as an input, the determined defectivity quantifier (250) for the lithographical circuit fabrication process performed with the off-target value (220) for the process parameter.
  6. The method of any of claims 1-4, wherein extrapolating comprises applying a predetermined analytical dependence between the defectivity quantifier for the lithographical circuit fabrication process and the process parameter in order to determine the defectivity quantifier (310) for the lithographical circuit fabrication process performed with the target value (210) for the process parameter.
  7. The method of any of claims 1-6, comprising modifying the target value (210) of the process parameter to increase an occurrence rate of the stochastic effect.
  8. A system (100) comprising: a quantifier determination engine (110) configured to determine a defectivity quantifier (310) for a lithographical circuit fabrication process performed with a target value (210) for a process parameter of the lithographical circuit fabrication process, wherein the defectivity quantifier (250, 310) specifies a quantitative value for a stochastic effect on the lithographical circuit fabrication process, the system (100) further comprising a computing system for: modifying the target value (210) for the process parameter to obtain an off-target value (220) for the process parameter; determining a defectivity quantifier (250) for the lithographical circuit fabrication process performed with the off-target value (220) for the process parameter; and determining the defectivity quantifier (310) for the lithographical circuit fabrication process performed with the target value (210) for the process parameter by extrapolating from the determined defectivity quantifier (250) for the lithographical circuit fabrication process performed with the off-target value (220) for the process parameter; and the system (100) further comprising a quantifier provision engine (112) configured to provide the determined defectivity quantifier (310) for the lithographical circuit fabrication process performed with the target value (210) for the process parameter for assessment of the lithographical circuit fabrication process.
  9. The system (100) of claim 8, wherein the stochastic effect comprises a particular stochastic-induced defect in circuits manufactured via the lithographical circuit fabrication process with the target value (210) for the process parameter and wherein the defectivity quantifier (250, 310) comprises a defect probability for the particular stochastic-induced defect.
  10. The system (100) of claim 8 or 9, wherein the quantifier determination engine (110) is configured to determine the defectivity quantifier (250) for the lithographical circuit fabrication process performed with the off-target value (220) for the process parameter through stochastic simulations, experimental measurements, or a combination of both.
  11. The system (100) of any of claims 8-10, wherein the quantifier determination engine (110) is configured to modify the target value (210) for the process parameter by adjusting a dose value, a focus value, a photoresist parameter values, a photomask dimension value of exposed features, or any combination thereof.
  12. The system (100) of any of claims 8-11, wherein the quantifier determination engine (110) is configured to extrapolate the defectivity quantifier (310) for the lithographical circuit fabrication process performed with the target value (210) by: applying a logarithmic curve-fitting extrapolation process using, as an input, the determined defectivity quantifier (250) for the lithographical circuit fabrication process performed with the off-target value (220) for the process parameter.
  13. The system (100) of any of claims 8-11, wherein the quantifier determination engine (110) is configured to extrapolate the defectivity quantifier (310) for the lithographical circuit fabrication process performed with the target value (210) by: applying a predetermined analytical dependence between the defectivity quantifier for the lithographical circuit fabrication process and the process parameter in order to determine the defectivity quantifier (310) for the lithographical circuit fabrication process performed with the target value (210) for the process parameter.
  14. The system (100) of any of claims 8-13, wherein the quantifier determination engine (110) is configured to modify the target value (210) of the process parameter to increase an occurrence rate of the stochastic effect.
  15. A non-transitory machine-readable medium (520) comprising instructions (522, 524) that, when executed by a processor (510), cause a computing system (500) to perform a method according to any of claims 1-7.

Description

BACKGROUND Electronic circuits, such as integrated circuits, are used in nearly every facet of modern society, from automobiles to microwaves to personal computers and more. Design of circuits may involve many steps, known as a "design flow." The particular steps of a design flow are often dependent upon the type of circuit being designed, its complexity, the design team, and the circuit fabricator or foundry that will manufacture the circuit. Electronic design automation (EDA) applications support the design and verification of circuits prior to fabrication. EDA applications may implement various procedures, e.g., functions, tools, or features to analyze, test, or verify a circuit design at various stages of the design flow. Further prior art may be found in WO 2020 / 114 684 A1 disclosing a method for analyzing a process, the method including: obtaining a multi-dimensional probability density function representing an expected distribution of values for a plurality of process parameters; obtaining a performance function relating values of the process parameters to a performance metric of the process; and using the performance function to map the probability density function to a performance probability function having the process parameters as arguments. BRIEF DESCRIPTION OF THE DRAWINGS Certain examples are described in the following detailed description and in reference to the drawings. Figure 1 shows an example of a computing system that supports defectivity quantifier determinations through off-target process parameters for lithographical circuit fabrication processes.Figure 2 shows an example determination of defectivity quantifiers for a lithographical circuit fabrication process performed with off-target values for process parameters.Figure 3, not forming part of the claimed subject matter, exemplary shows an example extrapolation of a defectivity quantifier for a lithographical circuit fabrication process performed with target values for process parameters from determined defectivity quantifiers for the lithographical circuit fabrication process performed with off-target values for the process parameters.Figure 4 shows an example of logic that a system may implement to support defectivity quantifier determinations through off-target process parameters for lithographical circuit fabrication processes.Figure 5 shows an example of a computing system that supports defectivity quantifier determinations through off-target process parameters for lithographical circuit fabrication processes. DETAILED DESCRIPTION In design flows for integrated circuits (ICs), a layout design may be derived from an electronic circuit design. The layout design may comprise an IC layout, an IC mask layout, or a mask design. In particular, the layout design may be a representation of an IC in terms of planar geometric shapes that correspond to the patterns of metal, oxide, or semiconductor layers which make up the components of the IC. The layout design can be for entire chip or a portion of a full-chip layout design. Lithography is a process used to manufacture electronic circuits in which light is used to transfer a geometric pattern from a photomask, based on the layout design, to a silicon substrate coated by a photo-sensitive resist material (photoresist). One common family of photoresists is composed of entangled polymer chains. The polymer may contain certain functional groups which become modified due to chemical reactions caused by exposure to light (deprotection) and hence affects the polymer's solubility during development, thus creating a mask for the subsequent etching process. Various types of lithographical circuit fabrication processes are possible today, including deep ultraviolet (DUV) lithography or extreme ultraviolet (EUV) lithography. In DUV or EUV lithography, stochastic phenomena may manifest during fabrication processes, such as line edge roughness or critical dimension (CD) nonuniformity. Stochastic effects may refer to random events or effects during fabrication that occur by chance in lithographical processes. Stochastic effects can cause pattern roughness or unintended characteristics in manufactured ICs. Different stochastic effects in lithographical fabrication processes can impact IC manufacture differently, and stochastic metrics may refer to any quantification of a stochastic effect. Examples of stochastic effects include line-edge roughness, sidelobe printing, sub-resolution assist feature (SRAF) printability, and others. In more extreme cases, stochastic effects may lead to circuit defects, e.g., stochastic pinching or bridging of the patterned features, resulting in potential failure of the electronic circuit. Other examples of stochastic-induced defects that can occur due to stochastic effects include ling breaks, missing contacts (also referred to as vias), kissing vias (e.g., merged contact holes), and more. DUV, EUV, or other lithographical circuit fabrication processes may be subject to