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EP-4376567-B1 - THREE-DIMENSIONAL FERROELECTRIC MEMORY DEVICE

EP4376567B1EP 4376567 B1EP4376567 B1EP 4376567B1EP-4376567-B1

Inventors

  • NAM, SEUNGGEOL
  • Heo, Jinseong
  • LEE, HYUNJAE
  • CHOE, DUKHYUN

Dates

Publication Date
20260506
Application Date
20231113

Claims (15)

  1. A three-dimensional, 3D, ferroelectric memory device (100) comprising: a substrate (105); a plurality of insulating layers (111) stacked on an upper surface of the substrate; a plurality of gate electrodes (170) between the plurality of insulating layers; a plurality of gate insulating layers (160) in contact with corresponding side surfaces of the plurality of gate electrodes; a ferroelectric layer (130) in contact with side surfaces of the plurality of insulating layers; a plurality of intermediate electrodes (120) between the plurality of gate insulating layers and the ferroelectric layer; and a channel layer (140) in contact with the ferroelectric layer.
  2. The 3D ferroelectric memory device of claim 1, wherein each of the plurality of intermediate electrodes is configured to include a charge of a first polarity.
  3. The 3D ferroelectric memory device of claim 1 or 2, wherein in a cross-sectional view, the plurality of gate electrodes are stacked in a direction perpendicular to the upper surface of the substrate, and each of the plurality of gate electrodes extends in a direction parallel to the upper surface of the substrate, and optionally wherein each of the plurality of gate electrodes is electrically connected to a word line, and each of the plurality of intermediate electrodes are configured to be a floating electrode.
  4. The 3D ferroelectric memory device of claim 1, 2 or 3, wherein the plurality of intermediate electrodes extend to protrude from side surfaces of the plurality of insulating layers in a first direction parallel to the upper surface of the substrate, and optionally wherein the ferroelectric layer and the channel layer each have a protruding shape corresponding to a protruding portion of the plurality of intermediate electrodes.
  5. The 3D ferroelectric memory device of claim 4, wherein the plurality of gate insulating layers are respectively on an upper surface, a lower surface, and a side surface of corresponding gate electrodes of the plurality of gate electrodes, the upper and lower surfaces of the corresponding gate electrodes parallel to the upper surface of the substrate, and the side surface of the corresponding gate electrodes perpendicular to upper surface the substrate.
  6. The 3D ferroelectric memory device of claim 4, wherein the plurality of gate insulating layers are respectively on one side surface of corresponding gate electrodes of the plurality of gate electrodes.
  7. The 3D ferroelectric memory device of claim 4, wherein a source electrode and a drain electrode are respectively on both sides of the channel layer in a second direction that is parallel to the substrate and perpendicular to the first direction, and optionally wherein the source electrode is electrically connected to a corresponding source line, and the drain electrode is electrically connected to a corresponding bit line.
  8. The 3D ferroelectric memory device of any preceding claim, wherein, in a cross-sectional view, the plurality of intermediate electrodes extend towards side surfaces of the plurality of insulating layers in a first direction parallel to the upper surface the substrate.
  9. The 3D ferroelectric memory device of claim 8, wherein the plurality of gate insulating layers are respectively on an upper surface, a lower surface, and the side surface of corresponding gate electrodes of the plurality of gate electrodes, the upper and lower surfaces of the corresponding gate electrodes parallel to the upper surface of the substrate, and the side surface of the corresponding gate electrodes being perpendicular to the upper surface of the substrate.
  10. The 3D ferroelectric memory device of claim 8, wherein the plurality of gate insulating layers are respectively on the side surface of the corresponding gate electrodes.
  11. The 3D ferroelectric memory device of any preceding claim, wherein each of the plurality of gate electrodes and each of the plurality of intermediate electrodes independently include at least one of W, TiN, TaN, WN, NbN, Mo, Ru, Ir, RuO, IrO, or polysilicon.
  12. The 3D ferroelectric memory device of any preceding claim, wherein the insulating layers comprise at least one of SiO, SiOC, SiON, or SiN.
  13. The 3D ferroelectric memory device of any preceding claim, wherein the ferroelectric layers comprise at least one of a ferroelectric fluorite-based material, a ferroelectric nitride-based material, or a ferroelectric perovskite.
  14. The 3D ferroelectric memory device of any preceding claim, wherein the gate insulating layers comprise at least one of SiO, SiN, AlO, HfO, or ZrO, and optionally wherein the channel layer is provided to correspond with the plurality of gate electrodes, and further optionally wherein the channel layer comprises at least one of a Group IV semiconductor, a Group III-V semiconductor, an oxide semiconductor, a nitride semiconductor, a nitrogen oxide semiconductor, a two-dimensional (2D) semiconductor material, quantum dots, or an organic semiconductor.
  15. The 3D ferroelectric memory device of any preceding claim, wherein the channel layer extends in a direction perpendicular to the upper surface of the substrate.

Description

FIELD OF THE INVENTION The disclosure relates to a three-dimensional (3D) ferroelectric memory device. BACKGROUND OF THE INVENTION Demand for reliable solid-state drives (SSDs) has increased as hard disks have been replaced with solid-state drives (SSDs), and thus, demand for NAND flash memory devices, which are nonvolatile memory devices, has also increased. Recently, due to the requirements for highly integrated memory devices of compact sizes, a three-dimensional (3D) NAND flash memory device having a plurality of memory cells stacked on a substrate in a perpendicular direction has been developed. In addition, research is currently in progress into the application of a ferroelectric field-effect transistor (FeFET), which has advantages such as a low operating voltage and a high programming rate, to 3D NAND flash memory devices. US 2020/020704 A1 describes a non-volatile memory system that includes a plurality of NAND strings of non-volatile storage elements. Said 3D ferroelectric memory comprises a plurality of word lines, a tunneling layer in contact with side surfaces of the word lines, a ferroelectric layer and a charge storage layer between the tunneling layer and the ferroelectric layer. WO 2022/239957 A1 describes a three-dimensional flash memory comprising stack structures, each comprising interlayer insulation films and gate electrodes, which extend in the horizontal direction and are alternately stacked in the vertical direction. SUMMARY OF THE INVENTION Provided are three-dimensional (3D) ferroelectric memory devices. Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments of the disclosure. According to an aspect of the disclosure, there is provided a 3D ferroelectric memory device according to claim 1. Each of the plurality of intermediate electrodes may be configured to include a charge of a first polarity. The plurality of gate electrodes, when viewed in a cross-sectional view, may be stacked in a direction perpendicular to the upper surface of the substrate, and each of the plurality of gate electrodes may extend in a direction parallel to the upper surface of the substrate. Each of the plurality of gate electrodes may be electrically connected to a word line, and each of the plurality of intermediate electrodes may be configured to be a floating electrode. The plurality of intermediate electrodes may extend to protrude from side surfaces of the plurality of insulating layers in a first direction parallel to the upper surface of the substrate. The ferroelectric layer and the channel layer may each have a protruding shape corresponding to a protruding portion of the plurality of intermediate electrodes. The plurality of gate insulating layers may be respectively provided on an upper, a lower surface, and a side surface of the plurality of gate electrodes, the upper and lower surfaces of the corresponding gate electrodes parallel to the upper surface of the substrate, and the side surface of the corresponding gate electrodes perpendicular to upper surface the substrate. The plurality of gate insulating layers may be respectively on one side surface of corresponding gate electrodes of the plurality of gate electrodes. A source electrode and a drain electrode may be respectively on both sides of the channel layer in a second direction that is parallel to the substrate and perpendicular to the first direction. The source electrode may be electrically connected to a corresponding source line, and the drain electrode may be electrically connected to a corresponding bit line. The plurality of intermediate electrodes may, in a cross-sectional view, extend towards side surfaces of the plurality of insulating layers in a first direction parallel to the upper surface the substrate. The plurality of gate insulating layers may be respectively on an upper surface, a lower surface, and the side surface of corresponding gate electrodes of the plurality of gate electrodes, the upper and lower surfaces of the corresponding gate electrodes parallel to the upper surface of the substrate, and the side surface of the corresponding gate electrodes being perpendicular to the upper surface of the substrate. The plurality of gate insulating layers may be respectively on the side surface of the corresponding gate electrode. Each of the plurality of gate electrodes and each i of the plurality of intermediate electrodes may independently include at least one of W, TiN, TaN, WN, NbN, Mo, Ru, Ir, RuO, IrO, or polysilicon. The insulating layers may include at least one of SiO, SiOC, or SiON. The ferroelectric layers may include a ferroelectric fluorite-based material, a ferroelectric nitride-based material, or a ferroelectric perovskite. The gate insulating layers may include at least one of SiO, SiN, AlO, HfO, or ZrO. The channel layer may extend in a direction perpendicular to the upper s