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EP-4394774-B1 - STORAGE SYSTEM, CONTROLLER, MEMORY AND OPERATION METHOD, AND ELECTRONIC DEVICE

EP4394774B1EP 4394774 B1EP4394774 B1EP 4394774B1EP-4394774-B1

Inventors

  • TAN, HUA
  • GAO, YAOLONG

Dates

Publication Date
20260506
Application Date
20221118

Claims (14)

  1. A controller (110, 310) that is coupled to a memory (120, 220, 320) with each memory cell of the memory (120, 220, 320) being used for storing m-bit information, where m is a positive integer greater than 1, and the controller (110, 310) including at least one of an exclusive OR circuit (311), an inverter (312) and an access circuit (313); the controller (110, 310) is used for receiving n groups of logic page data, and generating, at different values of m and n, at least one group of logic page data selectively by the at least one of the exclusive OR circuit (311), the inverter (312) and the access circuit (313), where n is a positive integer that is less than m; and the controller (110, 310) is further used for transmitting m groups of logic page data to the memory (120, 220, 320) to generate 2 m different data states in the memory (120, 220, 320), the m groups of logic page data including the n groups of logic page data and the generated at least one group of logic page data, and the m groups of logic page data comprising m-bit information of a group of memory cells (109, 110), wherein a difference value between m and n is at least 2, and the controller is further configured to generate at least one of the additional groups of logic page data by the access circuit as a filling-type group, the filling type comprising an all-0 sequence or an all-1 sequence.
  2. The controller (110, 310) of claim 1, wherein the exclusive OR circuit (311) comprises a redundant arrays of independent disks (RAID) exclusive OR circuit (311) in the controller (110, 310).
  3. The controller (110, 310) of claim 1, wherein the access circuit (313) comprises a direct memory access circuit (313) in the controller (110, 310).
  4. The controller (110, 310) of claim 1, wherein the circuit selected by the controller (110, 310) comprises the exclusive OR circuit (311), and the controller (110, 310) being used for performing an exclusive OR operation on the n groups of logic page data by the exclusive OR circuit (311) to obtain a first group of logic page data
  5. The controller (110, 310) of claim 1, wherein the circuit selected by the controller (110, 310) comprises the exclusive OR circuit (311) and the inverter (312), and the controller (110, 310) being used for performing an exclusive OR operation on the n groups of logic page data by the exclusive OR circuit (311) to obtain intermediate data, and performing a NOT operation on the intermediate data by the inverter (312) to obtain the first group of logic page data,
  6. The controller (110, 310) of claim 5,wherein the circuit selected by the controller (110, 310) further comprises the access circuit (313), and the controller (110, 310) being further used for determining a filling type of a second group of logic page data by the access circuit (313) and determining the second group of logic page data from the filling type, wherein the at least one group of logic page data includes the second group of logic page data.
  7. The controller (110, 310) of claim 1, wherein the circuit selected by the controller (110, 310) comprises the access circuit (313), and the controller (110, 310) being used for copying a group of logic page data in the n groups of logic page data by the access circuit (313) to obtain a first group of logic page data.
  8. The controller (110, 310) of claim 7, wherein the controller (110, 310) is further used for determining a filling type of a second group of logic page data by the access circuit (313) and determining the second group of logic page data from the filling type, wherein the at least one group of logic page data includes the second group of logic page data.
  9. A memory system (100, 300) comprising: a controller (110, 310) according to one of the previous claims; and a memory (120, 220, 320) coupled to the controller (110, 310), each memory cell of the memory (120, 220, 320) being used for storing m-bit information, where m is a positive integer greater than 1.
  10. An operation method of a memory system (100, 300) that is applied to a memory system (100, 300) comprising a controller (110, 310) and a memory (120, 220, 320) coupled to the controller (110, 310), and each memory cell of the memory (120, 220, 320) being used for storing m-bit information, where m is a positive integer greater than 1, and the method comprises: receiving n groups of logic page data, and generating, at different values of m and n, at least one group of logic page data selectively by at least one of an exclusive OR circuit (311), an inverter (312) and an access circuit (313), where n is a positive integer and being less than m, wherein a difference value between m and n is 2; and transmitting m groups of logic page data to the memory (120, 220, 320) to generate 2 m different data states in the memory (120, 220, 320), the m groups of logic page data comprising the n groups of logic page data and the generated at least one group of logic page data, and the m groups of logic page data comprising m-bit information of a group of memory cells (109, 110), wherein generating the at least one group of logic page data comprises selecting the access circuit (313), and determining, by the access circuit (313), a filling type of a second group of logic page data and determining the second group of logic page data from the filling type, the filling type comprising an all-1 sequence.
  11. The operation method of the memory system (100, 300) of claim 10 , wherein the exclusive OR circuit (311) comprises a redundant array of independent disks (RAID) exclusive OR circuit (311) in the controller (110, 310).
  12. The operation method of the memory system (100, 300) of claim 10, wherein the access circuit (313) comprises a direct memory access circuit in the controller (110, 310).
  13. The operation method of the memory system (100, 300) of claim 10, wherein generating the at least one group of logic page data selectively by the at least one of the exclusive OR circuit (311), the inverter (312) and the access circuit (313) comprises: selecting the exclusive OR circuit (311), and performing an exclusive OR operation on the n groups of logic page data by the exclusive OR circuit (311) to obtain a first group of logic page data.
  14. The operation method of the memory system (100, 300) of claim 10 , wherein generating the at least one group of logic page data selectively by the at least one of the exclusive OR circuit (311), the inverter (312) and the access circuit (313) comprises: selecting the exclusive OR circuit (311) and the inverter (312), and performing an exclusive OR operation on the n groups of logic page data by the exclusive OR circuit (311) to obtain intermediate data, and performing a NOT operation on the intermediate data by the inverter (312) to obtain the first group of logic page data.

Description

TECHNICAL FIELD Implementations of the present disclosure relate to, but are not limited to, the field of semiconductors, and in particular, to a memory system, a controller and operation methods thereof. BACKGROUND With the development of flash memory devices (NAND) of computers, the number of bits stored in a memory cell in this type of memories has increased from 1 bit to 2 bits, 3 bits or 4 bits, etc. Accordingly, the memory cell has evolved from a Single Level Cell (SLC) to a Multiple Level Cell (MLC), a Triple Level Cell (TLC), or a Quad-Level Cell (QLC). The greater the number of bits a memory cell of the memory stores, the larger its storage capacity and the lower its cost, while its write speed is slower and is less reliable. Currently, in some disclosures, a NAND memory is required to combine both the fast write speed and high reliability of a single level cell and the high storage capacity and low cost of a multiple level cell. Therefore, how to flexibly configure the NAND memory to enable the same to implement multiple memory cell modes has become a technical problem to be solved. US 2022/0 189 544 A1 discloses data programming techniques to store multiple bits of data per memory cell with high reliability. SUMMARY The invention is set out in the appended set of claims. The dependent claims set out particular embodiments. In view of this, embodiments of the present disclosure provide a memory system, a controller and operation methods thereof, and an electronic device, solving the problem of difficulty in flexibly configuring a NAND memory to enable the same to implement multiple memory cell modes. In a first aspect of the disclosure, a memory system is provided that can include a controller according to the second aspect and a memory coupled to the controller, and each memory cell of the memory being used for storing m-bit information, wherein m being a positive integer greater than 1. In the above technical solution, the controller is used for generating at least one group of logic page data selectively by the at least one of the exclusive OR circuit, the inverter and the access circuit, and transmitting the at least one group of logic page data and the n groups of logic page data received to the memory to generate 2n different data states in the memory, that is, a part of memory space of the memory may be used as at least one of an SLC, an MLC, a TLC and a QLC. In this way, the NAND memory can be flexibly configured to enable the same to implement multiple memory cell modes, and can simultaneously have the advantages of fast write speed, high reliability, high storage capacity and low cost and the like. Further, compared with having the Central Processing Unit (CPU) in the controller perform logical operations, in the embodiments of the present disclosure, it is a simpler scheme that generates the at least one group of logic page data by the at least one of hardware modules such as the exclusive OR circuit, the inverter, the access circuit and the like in the controller. While multiple memory cell modes are implemented, it helps to improve the operational efficiency of the memory system. Moreover, compared with the scheme of developing a universal NAND memory, the scheme in which the memory system provided by the embodiments of the present disclosure uses the hardware modules is more friendly, and can be compatible with the existing NAND protocol, thereby being helpful to reduce the development costs. In one possible implementation of the first aspect, the exclusive OR circuit includes a redundant arrays of independent disks (RAID) exclusive OR circuit in the controller. In the above possible implementation, an original redundant arrays of independent disks (RAID) exclusive OR circuit is reused without adding a new exclusive OR circuit in the controller. Therefore, the at least one group of logic page data can be generated at a lower hardware cost. A foundation is provided for implementing multiple memory cell modes of the memory and improving the operation efficiency of the memory system. In one possible implementation of the first aspect, the access circuit includes a direct memory access circuit in the controller. In the above possible implementation, an original direct memory access (DMA) circuit is reused without adding a new access circuit in the controller. Therefore, the at least one group of logic page data can be generated at a lower hardware cost. A foundation is provided for implementing multiple memory cell modes of the memory and improving the operation efficiency of the memory system. In one possible implementation of the first aspect, the circuit selected by the controller includes the exclusive OR circuit, and the controller being used for performing an exclusive OR operation on the n groups of logic page data by the exclusive OR circuit to obtain a first group of logic page data. In the above possible implementation, the controller is used for performing an exclusive OR oper