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EP-4394876-B1 - DEVICE FOR ELECTROSTATIC DISCHARGE PROTECTION USING SILICON CONTROLLED RECTIFIER

EP4394876B1EP 4394876 B1EP4394876 B1EP 4394876B1EP-4394876-B1

Inventors

  • DO, KYOUNGIL
  • JUNG, JINWOO
  • SONG, JOOYOUNG
  • LEE, Mijin
  • JEON, CHANHEE

Dates

Publication Date
20260506
Application Date
20231227

Claims (9)

  1. A device (10) comprising a first clamp circuit (70a) connected between a first node (N1) and a second node (N2), wherein the first clamp circuit (70a) comprises: a symmetric bipolar transistor (Qpnp) comprising a control terminal, a first current terminal and a second current terminal, wherein the first current terminal and the second current terminal are symmetrical to each other with respect to the control terminal; a first bipolar transistor (Qn1) electrically connected to the symmetric bipolar transistor (Qpnp) and to the first node (N1); and a second bipolar transistor (Qn2) electrically connected to the symmetric bipolar transistor (Qpnp) and to the second node (N2), wherein the first bipolar transistor (Qn1) comprises a first collector electrically connected to the control terminal, a first base electrically connected to the first current terminal, and a first emitter electrically connected to the first node (N1), wherein the second bipolar transistor (Qn2) comprises a second collector electrically connected to the control terminal, a second base electrically connected to the second current terminal, and a second emitter electrically connected to the second node (N2), wherein the first current terminal corresponds to a first p-well (PW1), the control terminal corresponds to a first n-well (NW2), and the second current terminal corresponds to a second p-well (PW2), wherein the first p-well (PW1), the first n-well (NW2), and the second p-well are sequentially disposed, wherein each of the first bipolar transistor (Qn1) and the second bipolar transistor (Qn2) is an NPN bipolar transistor, wherein the first collector corresponds to the first n-well (NW2), the first base corresponds to the first p-well (PW1), and the first emitter corresponds to an n+ region disposed in the first p-well (PW1), wherein the second collector corresponds to the first n-well (NW2), the second base corresponds to the second p-well (PW2), and the second emitter corresponds to an n+ region disposed in the second p-well (PW2), wherein the first clamp circuit (70a) further comprises: at least one first diode (Df) forwardly connected from the first node (N1) to the second current terminal; at least one second diode (Dr) forwardly connected from the second node (N2) to the first current terminal, a second n-well (NW1) which is apart from the first p-well (PW1), a third n-well (NW3) which is apart from the second p-well (PW2), and a n+ region (n1) which surrounds each of the second n-well (NW1) and the third n-well (NW3) and surrounds the first p-well (PW1), the first n-well (NW2), and the second p-well (PW2), wherein a cathode of the at least one first diode (Df) corresponds to the second n-well (NW 1) and an anode of the at least one first diode (Df) corresponds to a p+ region disposed in the second n-well (NW1), and wherein a cathode of the at least one second diode (Dr) corresponds to the third n-well, and an anode of the at least one second diode (Dr) corresponds to a p+ region disposed in the third n-well (NW3).
  2. The device (10) of claim 1, wherein the at least one first diode (Df) comprises a first-first diode (Df1), wherein a cathode of the first-first diode (Df1) corresponds to the second n-well (NW1), and an anode of the first-first diode (Df1) corresponds to the p+ region disposed in the second n-well (NW1), and wherein the at least one second diode (Dr) comprises a first-second diode (Dr1), wherein a cathode of the first-second diode (Dr1) corresponds to the third n-well, and an anode of the first-second diode (Dr1) corresponds to the p+ region disposed in the third n-well.
  3. The device (10) of claim 2, wherein the at least one first diode (Df) further comprises a second-first diode (Df2), wherein an anode of the second-first diode (Df2) corresponds to the first p-well (PW1), and a cathode of the second-first diode (Df2) corresponds to an n+ region disposed in the first p-well (PW1), and wherein the at least one second diode (Dr) further comprises a second-second diode (Dr2), wherein an anode of the second-second diode (Dr2) corresponds to the second p-well (PW2), and a cathode of the second-second diode (Dr2) corresponds to an n+ region disposed in the second p-well (PW2).
  4. The device (10) of claim 1, wherein the first clamp circuit (70a) further comprises: at least one first diode (Df) forwardly connected from the control terminal to the first node (N1); and at least one second diode (Dr) forwardly connected from the control terminal to the second node (N2).
  5. The device (10) of claim 1, wherein the first clamp circuit (70a) further comprises: at least one first diode (Df) forwardly connected from the control terminal to the first current terminal; and at least one second diode (Dr) forwardly connected from the control terminal to the second current terminal.
  6. The device (10) of claim 1, wherein the first p-well (PW1), the first n-well (NW2), and the second p-well (PW2) are disposed in a deep n-well which is disposed in a substrate.
  7. A device (10) comprising a first clamp circuit (70b) connected between a first node (N1) and a second node (N2), wherein the first clamp circuit (70b) comprises: a symmetric bipolar transistor (Qnpn) comprising a control terminal, a first current terminal and a second current terminal, wherein the first current terminal and the second current terminal are symmetrical to each other with respect to the control terminal; a first bipolar transistor (Qp1) electrically connected to the symmetric bipolar transistor (Qnpn) and to the first node (N1); a second bipolar transistor (Qp2) electrically connected to the symmetric bipolar transistor (Qnpn) and to the second node (N2), wherein the first bipolar transistor (Qp1) comprises a first collector electrically connected to the control terminal, a first base electrically connected to the first current terminal, and a first emitter electrically connected to the first node (N1), wherein the second bipolar transistor (Qp2) comprises a second collector electrically connected to the control terminal, a second base electrically connected to the second current terminal, and a second emitter electrically connected to the second node (N2), wherein the first current terminal corresponds to a first n-well (NW2), the control terminal corresponds to a p-well (PW), and the second current terminal corresponds to a second n-well (NW3), wherein the first n-well (NW2), the p-well (PW), and the second n-well (NW3) are sequentially disposed, wherein each of the first bipolar transistor (Qp1) and the second bipolar transistor (Qp2) is a PNP bipolar transistor, wherein the first collector corresponds to the p-well (PW), the first base corresponds to the first n-well (NW2), and the first emitter corresponds to a p+ region disposed in the first n-well (NW2), wherein the second collector corresponds to the p-well (PW), the second base corresponds to the second n-well (NW3), and the second emitter corresponds to a p+ region disposed in the second n-well (NW3), wherein the first clamp circuit (70b) further comprises: at least one first diode (Df) forwardly connected from the first current terminal to the second node (N2); at least one second diode (Dr) forwardly connected from the second current terminal to the first node (N1), a third n-well (NW1) which is apart from the first n-well (NW2), a fourth n-well (NW4) which is apart from the third n-well (NW3), and a first p+ region (p1) which surrounds each of the third n-well (NW1) and the fourth n-well (NW4) and surround the first n-well (NW2), the p-well (PW), and the second n-well (NW3), wherein a cathode of the at least one first diode (Df) corresponds to the third n-well (NW1) and an anode of the at least one first diode (Df) corresponds to a p+ region disposed in the third n-well (NW1), and wherein a cathode of the at least one second diode (Dr) corresponds to the fourth n-well (NW4), and an anode of the at least one second diode (Dr) corresponds to a p+ region disposed in the fourth n-well (NW4).
  8. The device (10) of claim 7, wherein the first clamp circuit (70a, 70b) further comprises: at least one first diode (Df) forwardly connected from the first current terminal to the control terminal; and at least one second diode (Dr) forwardly connected from the second current terminal to the control terminal.
  9. The device (10) of claim 1 or claim 7, further comprising: a second clamp circuit connected between the second node (N2) and a third node, and having a same structure as the first clamp circuit (70a, 70b); and an input/output pad electrically connected to the second node (N2), wherein the first node (N1) is connected to a positive supply voltage node, wherein the second node (N2) is connected to a negative supply voltage node, and wherein the symmetric bipolar transistor (Qpnp, Qnpn) of the first clamp circuit (70a, 70b) shares a well with a symmetric bipolar transistor (Qpnp, Qnpn) of the second clamp circuit.

Description

BACKGROUND 1. Field The disclosure relates to a device for electrostatic discharge protection, and more particularly, to a device for electrostatic discharge protection using a silicon controlled rectifier. 2. Description of Related Art Electrostatic discharge (ESD) may cause an integrated circuit to malfunction or even damage the integrated circuit. Accordingly, an integrated circuit may include a component for ESD protection, which may protect an internal circuit from ESD which has occurred outside the integrated circuit. According to the development of semiconductor process, sizes of elements included in an integrated circuit may be reduced, and operating voltages of elements included in an integrated circuit may decrease for reduced power consumption. In addition, frequencies of signals input to or output from an integrated circuit may increase for high performance. Accordingly, there is a need for components for ESD protection to have improved performance. US 2010/109631 A1 discloses the following: A tunable voltage isolation ground to ground ESD clamp is provided. The clamp includes a dual-direction silicon controlled rectifier (SCR) and trigger elements. The SCR is coupled between first and second grounds. The trigger elements are also coupled between the first and second grounds. Moreover, the trigger elements are configured to provide a trigger current to the dual-direction silicon controlled rectifier when a desired voltage between the first and second grounds is reached. US 2002/074604 A1 discloses the following: A two terminal ESD protection structure formed by an alternating arrangement of adjacent p-n-p-n-p semiconductor regions provides protection against both positive and negative ESD pulses. When an ESD pulse appears across the two terminals of the ESD protection structure, one of the inherent n-p-n-p thyristors is triggered into a snap-back mode thereby to form a low impedance path to discharge the ESD current. Some embodiments of the ESD protection structure of the present invention have an enhanced current handling capability and are formed by combining a number of standard cells. The standard cells include a corner cell, a center cell and an edge cell which are arranged adjacent each other to form an ESD protection structure which provides for current flow from across many locations therein. Some embodiments of the ESD protection structure of the present invention include a network consisting of a pair of current sources, e.g. back-to-back zener diodes, each connected in series with a resistor to control the trigger voltage of the ESD protection structure. US 2014/332843 A1 discloses the following: Junction-isolated blocking voltage devices and methods of forming the same are provided. In certain implementations, a blocking voltage device includes an anode terminal electrically connected to a first p-well, a cathode terminal electrically connected to a first n-well, a ground terminal electrically connected to a second p-well, and an n-type isolation layer for isolating the first p-well from a p-type substrate. The first p-well and the first n-well operate as a blocking diode. The blocking voltage device further includes a PNPN silicon controlled rectifier (SCR) associated with a P+ region formed in the first n-well, the first n-well, the first p-well, and an N+ region formed in the first p-well. Additionally, the blocking voltage device further includes an NPNPN bidirectional SCR associated with an N+ region formed in the first p-well, the first p-well, the n-type isolation layer, the second p-well, and an N+ region formed in the second p-well. CN 102 569 360 A discloses the following: The document discloses a bidirectional triode thyristor based on diode auxiliary triggering, which comprises a P substrate layer and two diode links, wherein a first N well, a P well and a second N well are arranged on the P substrate layer; a first N plus active implantation area, a first P plus active implantation area and a second N plus active implantation area are arranged on the first N well; a third N plus active implantation area, a second P plus active implantation area and a fourth N plus active implantation area are arranged on the second N well; and the third N plus active implantation area is connected with the anode of a first diode link, and the second N plus active implantation area is connected with the anode of a second diode link. The bidirectional triode thyristor utilizes diodes as auxiliary triggering units, so the thyristor has adjustable and lower forward and reverse breakdown voltages, can be suitable to on-chip electronic static discharge (ESD) protection in a deep sub-micron technology, and can be particularly suitable to the ESD protection and application of a plurality of mixing voltage interface circuits or different power supply areas. SUMMARY The scope of the invention is defined by the appended claims. Provided is a device for ESD protection which uses a silicon controlled