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EP-4398250-B1 - VOLTAGE SUPPLY CIRCUIT, MEMORY DEVICE INCLUDING THE SAME, AND OPERATING METHOD OF MEMORY DEVICE

EP4398250B1EP 4398250 B1EP4398250 B1EP 4398250B1EP-4398250-B1

Inventors

  • YOON, JAYANG
  • KIM, CHIHYUN
  • NAM, SANGWAN
  • YOON, CHIWEON
  • CHOI, HYEONGDO

Dates

Publication Date
20260506
Application Date
20240103

Claims (15)

  1. A voltage supply circuit (100) of a memory device (10), the voltage supply circuit (100) comprising: a first charging terminal (110) configured to supply a first voltage (VPPL) to charge at least one word line (WL) or the at least one bit line (BL); a second charging terminal (130) configured to supply a second voltage (VPPX) to charge the at least one word line (WL) or the at least one bit line (BL) based on supply of the first voltage (VPPL) by the first charging terminal (110) being stopped, wherein the second charging terminal (130) is configured to start supplying the second voltage (VPPX) based on a charged voltage of the at least one word line (WL) or the at least one bit line (BL), charged based on the first voltage (VPPL), satisfying a first reference condition, and wherein the second voltage (VPPX) is greater than the first voltage (VPPL).
  2. The voltage supply circuit of claim 1, wherein the second charging terminal (130) is configured to supply the second voltage (VPPX) based on a voltage of at least one word line (WL) or the at least one bit line (BL) having the same voltage as the first voltage (VPPL).
  3. The voltage supply circuit (100) of claim 1 or 2, further comprising: a first switch (120) connected to the first charging terminal (110); and a second switch (140) connected to the second charging terminal (130), wherein based on the charged voltage of the at least one word line (WL) or the at least one bit line (BL), charged based on the first voltage (VPPL), being determined to satisfy the first reference condition, the first switch (120) is configured to be changed to an open state, and the second switch (140) is configured to be changed to a closed state.
  4. The voltage supply circuit (100) of any preceding claim, further comprising a counter (180b) configured to count a supply time of the first voltage (VPPL), wherein the second charging terminal (130) is configured to supply the second voltage (VPPX) based on the supply time of the first voltage (VPPL) counted by the counter (180b) satisfying a reference supply time.
  5. The voltage supply circuit (100) of claim 3, further comprising a current sensor (180c) configured to detect intensity of an electric current passing through the first switch (120) and the second switch (140), wherein the second charging terminal (130) is configured to supply the second voltage (VPPX) based on intensity of a first current passing through the first switch (120) being determined to satisfy a reference current.
  6. The voltage supply circuit (100) of claim 5, wherein the second charging terminal (130) is configured to supply the second voltage (VPPX) based on an average intensity of the first current being determined to satisfy a first reference current.
  7. The voltage supply circuit (100) of claim 5, wherein the second charging terminal (130) is configured to stop supplying the second voltage (VPPX) based on an average intensity of a second current passing through the second switch (140) being determined to satisfy a first reference current.
  8. The voltage supply circuit (100) of claim 5, wherein the second charging terminal (130) is configured to start supplying the second voltage (VPPX) based on a maximum value of the first current being determined to satisfy a second reference current.
  9. The voltage supply circuit (100) of claim 5, wherein the second charging terminal (130) is configured to stop supplying the second voltage (VPPX) based on a maximum value of the second current passing through the second switch (130) being determined to satisfy a second reference current.
  10. A memory device (10) comprising the voltage supply circuit (100) of any preceding claim.
  11. An operating method of a memory device (10), the method comprising: supplying (S910), by a first charging terminal (110), a first voltage (VPPL) to charge at least one word line (WL) or at least one bit line (BL); supplying (S940), by a second charging terminal (130) a second voltage (VPPX) to charge the at least one word line (WL) or the at least one bit line (BL); and setting the second voltage (VPPX) as a value greater than the first voltage (VPPL), wherein supply of the second voltage (VPPX) starts based on a charged voltage of the at least one word line (WL) or the at least one bit line (BL), charged based on the first voltage (VPPL), satisfying a first reference condition.
  12. The method of claim 11, further comprising: supplying the second voltage (VPPX) when a voltage of at least one word line (WL) or the at least one bit line (BL) has the same voltage as the first voltage (VPPL).
  13. The method of claim 11 or 12, further comprising controlling (S910) a first switch (120) connected to the first charging terminal (110) and a second switch (140) connected to the second charging terminal (130) such that based in the charged voltage of the at least one word line (WL) or the at least one bit line (BL) being determined to satisfy a first reference condition, the first switch (120) is changed to an open state, and the second switch (140) is changed to a closed state.
  14. The method of any of claims 11 to 13, further comprising: detecting (S1020) a supply time of the first voltage (VPPL); and controlling the second voltage (VPPX) to be supplied based on the supply time of the first voltage (VPPL) being determined to satisfy a reference supply time.
  15. The method of claim 13, further comprising: detecting (S1120) intensity of electric currents passing through the first switch (120) and the second switch (140); and supplying (S1140) the second voltage (VPPX) when a first current passing through the first switch (120) is determined to satisfy a reference current.

Description

BACKGROUND 1. Field Embodiments of the disclosure relate to a voltage supply circuit, a memory device including the voltage supply circuit, and an operating method of the memory device, and more particularly, to a method of charging a word line or a bit line of the memory device. 2. Description of Related Art Recently, memory devices have been developed in the form of a three-dimensional device. As the number of stacked layers for the cell array increases in a 3D memory device, the charging capacity also increases. In a related art method of charging word lines or bit lines in a memory device, a voltage having a constant value is applied to the word lines or the bit lines. However, when the constant voltage is continuously applied, power consumption for charging word lines or bit lines is increased. Thus, in order to solve the above-described problem and/or other problems, it is necessary to develop a new technology for reducing power consumption in charging word lines or bit lines of a memory device. US 2021/0358553 A1 describes concurrent programming of multiple cells for non-volatile memory.US 2018/0204625 A1 describes a semiconductor memory device.US 2021/0050037 A1 describes a non-voltage memory apparatus, and a read and write method of the non-voltage memory apparatus. SUMMARY Embodiments of the disclosure provide a method of charging word lines or bit lines in which various constant voltages are applied in multiple charging stages, respectively. By applying voltages having different sizes at their own charging stages, an embodiment of the disclosure discloses a memory device for reducing the power consumption for charging the word lines or the bit lines. According to an aspect of the disclosure, there is provided a memory device including: a first charging terminal configured to supply a first voltage to at least one word line or the at least one bit line; and a second charging terminal configured to supply a second voltage to the at least one word line or the at least one bit line based on voltage supply by the first charging terminal being completed, wherein the second charging terminal is configured to start supplying the second voltage based on a charged voltage of the at least one word line or the at least one bit line charged based on the first voltage satisfying a first reference condition. According to another aspect of the disclosure, there is provided an operating method of a memory device, the method including: supplying, by a first charging terminal, a first voltage to at least one word line or at least one bit line; and supplying, by a second charging terminal a second voltage to the at least one word line or the at least one bit line, wherein supply of the second voltage starts based on a charged voltage of the at least one word line or the at least one bit line, charged based on the first voltage, satisfying a first reference condition. According to another aspect of the disclosure, there is provided a voltage supply circuit of a memory device, the voltage supply circuit including: a first charging terminal configured to supply a first voltage to at least one word line or the at least one bit line; a second charging terminal configured to supply a second voltage to the at least one word line or the at least one bit line based on supply of the first voltage by the first charging terminal being stopped, wherein the second charging terminal is configured to start supplying the second voltage starts based on a charged voltage of the at least one word line or the at least one bit line charged based on the first voltage satisfying a first reference condition. The embodiment of the claimed invention is as defined by the appended independent claims and preferred embodiments are defined by the appended dependent claims. BRIEF DESCRIPTION OF DRAWINGS Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which: FIG. 1 is a block diagram showing a memory device, according to an embodiment;FIG. 2 is a block diagram showing a voltage supply circuit of a memory device, according to an embodiment;FIG. 3 is a timing diagram illustrating voltage supply in multiple charging stages in an operating method of a memory device, according to an embodiment;FIG. 4 is a block diagram showing a voltage supply circuit of a memory device, according to an embodiment;FIG. 5 is a timing diagram showing voltage supply in multiple charging stages over time in an operating method of a memory device, according to an embodiment;FIG. 6 is a block diagram showing a voltage supply circuit of a memory device, according to an embodiment;FIGS. 7 and 8 are timing diagrams showing voltage supply in multiple charging stages according to the intensity of current in an operating method of a memory device, according to an embodiment;FIG. 9 is a flowchart showing a method of operating a memory device, according to an embodiment;FIG. 10 is a flowchart sh