Search

EP-4404262-B1 - DEVICE FOR ELECTROSTATIC DISCHARGE PROTECTION USING SILICON CONTROLLED RECTIFIER

EP4404262B1EP 4404262 B1EP4404262 B1EP 4404262B1EP-4404262-B1

Inventors

  • DO, KYOUNGIL
  • JUNG, JINWOO
  • SONG, JOOYOUNG
  • JEON, CHANHEE

Dates

Publication Date
20260506
Application Date
20231228

Claims (15)

  1. A device (10) comprising: a first clamp circuit (12) electrically connected between a first node (N1) and a second node (N2); and a second clamp circuit (13) electrically connected between the second node (N2) and a third node (N3), wherein the first clamp circuit (12) comprises: a first silicon controlled rectifier, SCR, 41 comprising a first region (n1) of a first conductivity type electrically connected to the first node (N1), a second region (p2) of a second conductivity type electrically connected to the first node (N1), a third region (n2) of the first conductivity type electrically connected to the second node (N2), and a fourth region (p3) of the second conductivity type electrically connected to the second node (N2); a first n-well (NW1); a first p-well (PW1); and a first gate electrode (G1) over a junction of the first n-well (NW1) and the first p-well (PW1) and over a channel region (CH1), wherein the channel region (CH1) comprises a junction of the second region (p2) and the third region (n2) between the first region (n1) and the fourth region (p3), wherein the first region (n1) and the second region (p2) are disposed in the first n-well (NW1); and the third region (n2) and the fourth region (p3) are disposed in the first p-well (PW1).
  2. The device (10) of claim 1, further comprising: a first resistor (R51) electrically connected to the first gate electrode (G1); and a first capacitor (C51) electrically connected to the first gate electrode (G1).
  3. The device (10) of claim 2, wherein the second clamp circuit (13) comprises a second SCR (42) and a second gate electrode (G2), wherein the first resistor (R51) is electrically connected between the first gate electrode (G1) and the first node (N1), wherein the first capacitor (C51) is electrically connected between the first gate electrode (G1) and the second node (N2), and wherein the device (10) further comprises: a second capacitor (C52) electrically connected between the second gate electrode (G2) and the second node (N2); and a second resistor electrically connected between the second gate electrode (G2) and the third node (N3).
  4. The device (10) of claim 2, wherein the second clamp circuit (13) comprises a second SCR (42) and a second gate electrode (G2), wherein the first resistor (R51) is electrically connected between the first gate electrode (G1) and the first node (N1), wherein the first capacitor (C51) is electrically connected between the first gate electrode (G1) and the second node (N2), and wherein the device (10) further comprises: a second resistor (R52) electrically connected between the second gate electrode (G2) and the second node (N2); and a second capacitor (C52) electrically connected between the second gate electrode (G2) and the third node (N3).
  5. The device (10) of claim 2, wherein the second clamp circuit (13) comprises a second SCR (42) and a second gate electrode (G2), wherein the first capacitor (C51) is electrically connected between the first gate electrode (G1) and the first node (N1), wherein the first resistor (R51) is electrically connected between the first gate electrode (G1) and the second node (N2), and wherein the device (10) further comprises: a second resistor electrically connected between the second gate electrode (G2) and the second node (N2); and a second capacitor (C52) electrically connected between the second gate electrode (G2) and the third node (N3).
  6. The device (10) of claim 2, wherein the second clamp circuit (13) comprises a second SCR (42) and a second gate electrode (G2), wherein the first resistor (R51) is electrically connected between the first gate electrode (G1) and the first node (N1), wherein the first capacitor (C110) is electrically connected between the first gate electrode (G1) and the second gate electrode (G2), and wherein the device (10) further comprises a second resistor electrically connected between the second gate electrode (G2) and the third node (N3).
  7. The device (10) of claim 2, wherein the second clamp circuit (13) includes a second SCR (42) and a second gate electrode (G2), wherein the first capacitor (C91) is electrically connected between the first gate electrode (G1) and the first node (N1), wherein the first resistor(R90) is electrically connected between the first gate electrode (G1) and the second gate electrode (G2), and wherein the device (10) further comprises a second capacitor (C92) electrically connected between the second gate electrode (G2) and the third node (N3).
  8. The device (10) of claim 2, wherein the second clamp circuit (13) comprises a second SCR (42) and a second gate electrode (G2), wherein the second gate electrode (G2) is electrically connected to the first gate electrode (G1), wherein the first capacitor (C51) is electrically connected between the first gate electrode (G1) and the first node (N1), wherein the first resistor (R51) is electrically connected between the first gate electrode (G1) and the second node (N2), and wherein the device (10) further comprises a second capacitor (C52) electrically connected between the second gate electrode (G2) and the third node (N3).
  9. The device (10) of claim 1, wherein the second clamp circuit (13) comprises a second SCR (42) and a second gate electrode (G2), wherein the device (10) further comprises a third clamp circuit electrically connected between the first node (N1) and the third node (N3), and wherein the first gate electrode (G1) and the second gate electrode (G2) are electrically connected to the third clamp circuit.
  10. The device (10) of claim 9, wherein the third clamp circuit (193a, 193b) comprises: A transistor (M19) comprising current terminals electrically connected to the first node (N1) and the third node (N3) respectively; a capacitor (C190) electrically connected between a control terminal of the transistor (M19) and the first node (N1); and a resistor (R190) electrically connected between the control terminal of the transistor (M19) and the third node (N3).
  11. The device (10) of claim 10, wherein the first gate electrode (G1) and the second gate electrode (G2) are electrically connected to the control terminal of the transistor (M19).
  12. The device (10) of claim 10, wherein the third clamp circuit (193b) further comprises an inverter (INV) having an input electrically connected to the control terminal of the transistor (M19), and wherein the first gate electrode (G1) and the second gate electrode (G2) are electrically connected to an output of the inverter (INV).
  13. The device (10) of claim 10, wherein the third clamp circuit (213a) further comprises an inverter (INV) having an input electrically connected to the control electrode of the transistor (M21), wherein the first gate electrode (G1) is electrically connected to an output of the inverter (INV), and wherein the second gate electrode (G2) is electrically connected to the control terminal of the transistor (M21).
  14. The device (10) of claim 9, wherein the third clamp circuit (213b) comprises: a transistor (M21) comprising a first current terminal electrically connected to the first node (N1) and a second current terminal electrically connected to the third node (N3); an inverter (INV) comprising an output electrically connected to a control terminal of the transistor (M21); a resistor (R210) electrically connected between the first node (N1) and an input of the inverter; and a capacitor (C210) electrically connected between the third node (N3) and the input of the inverter (INV).
  15. The device (10) of claim 9, further comprising: a fourth clamp circuit electrically connected between the first node (N1) and a fourth node; and a fifth clamp circuit electrically connected between the fourth node and the third node (N3), wherein a third gate electrode of the fourth clamp circuit and a fourth gate electrode of the fifth clamp circuit are electrically connected to the third clamp circuit.

Description

BACKGROUND The present disclosure relates to a device for protecting circuits from electrostatic discharge, and more particularly, to a device for electrostatic discharge protection using a silicon controlled rectifier. Electrostatic discharge (ESD) may cause malfunctions or even damage integrated circuits. Accordingly, an integrated circuit may include a component for ESD protection, and the component for ESD protection may protect an internal circuit from ESD generated from the outside of the integrated circuit. Due to the development of semiconductor processes, the size of elements included in integrated circuits may decrease, and the operating voltage of elements included in the integrated circuit may be reduced to reduce power consumption, and for higher performance, the frequency of signals input and output to the integrated circuit may be increased. Accordingly, components for ESD protection may be required to satisfy various requirements. US 2015/214210 A1 discloses the following: An electronic device includes a first device terminal and a second device terminal. A first and a second thyristor are reverse-connected between the two device terminals. A first and a second MOS transistor are respectively coupled between the conduction electrodes (emitters and collectors) of the two NPN transistors of the two thyristors. A third MOS transistor is coupled between the emitters of the two NPN bipolar transistors of the two thyristors and a fourth MOS transistor is coupled between the bases of the two PNP bipolar transistors of the two thyristors. A gate region is common to all the MOS transistors and a semiconductor substrate region includes the substrates of all the MOS transistors. US 2013/009204 A1 discloses the following: An ESD protection circuit includes a pad of an IC, circuitry coupled to the pad for buffering data, an RC power clamp on the IC, and first and second silicon controlled rectifier (SCR) circuits. The RC power clamp is coupled between a positive power supply terminal and a ground terminal. The first SCR circuit is coupled between the pad and the positive power supply terminal. The first SCR circuit has a first trigger input coupled to the RC power clamp circuit. The second SCR circuit is coupled between the pad and the ground terminal. The second SCR circuit has a second trigger input coupled to the RC power clamp circuit. At least one of the SCR circuits includes a gated diode configured to selectively provide a short or relatively conductive electrical path between the pad and one of the positive power supply terminal and the ground terminal. US 2016/056146 A1 discloses the following: An ESD protection circuit may include an STI-bound SCR and a gated SCR that may be electrically in parallel with the STI-bound SCR. The gated SCR may be perpendicular to the STI-bound SCR in a plane of the semiconductor substrate. The gated SCR may trigger more quickly and turn on more quickly than the STI-bound SCR. The STI-bound SCR may form the main current path for an ESD event. A low capacitive load with rapid response to ESD events may thus be formed. In an embodiment, the anode of the two SCRs may be shared. US 2002/050615 A1 discloses the following: A novel low-voltage-triggered semiconductor controlled rectified (LVTSCR) as an ESD protection device is provided in this document. The ESD protection device of the document has a lateral SCR (LSCR) structure with two electrodes and a MOS for triggering the LSCR. A dummy gate and a doped region are used to isolate the MOS from one of these two electrodes. The dummy gate is designed to block the formation of field-oxide layer formed in the device structure of the lateral SCR. Therefore, the proposed SCR device has a shorter current path in CMOS process, especially in the CMOS process with shallow trench isolation (STI) field-oxide layer. During an ESD, the current path in the ESD protection device is much shorter, and the turn-on speed and the ESD tolerance level are thereby enhanced. US 2008/088993 A1 discloses the following: A protection circuit comprises a first PNP-type bipolar transistor and a second NPN-type bipolar transistor, wherein the base of the first transistor is connected to the collector of the second transistor and the collector of the first transistor is connected to the base of the second transistor, and wherein a MOS transistor is connected between the collector and the emitter of the second transistor. SUMMARY Embodiments provide a device providing electrostatic discharge protection that meets various requirements using a silicon controlled rectifier. The scope of the invention is defined by the appended claims. According to an aspect of an example embodiment, a device includes: a first clamp circuit electrically connected between a first node and a second node; and a second clamp circuit electrically connected between the second node and a third node, wherein the first clamp circuit includes: a first silicon controlled rectifier (S