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EP-4418132-B1 - MASTER DEVICE TO COMMUNICATE WITH SLAVE DEVICE, SLAVE DEVICE, METHOD OF CONTROLLING THE SAME, AND DISPLAY DEVICE INCLUDING THE SAME

EP4418132B1EP 4418132 B1EP4418132 B1EP 4418132B1EP-4418132-B1

Inventors

  • HAN, DONG KWAN

Dates

Publication Date
20260506
Application Date
20231130

Claims (13)

  1. A master device (110) to communicate with a slave device (120), the master device (110) comprising: a first pad (PD1) connected to the slave device (120) through a first wire (WR1); a second pad (PD2) connected to the slave device (120) through a second wire (WR2); and a communication interface configured to transmit a communication control signal (CCTRL) to the slave device (120) through the first pad (PD1), and, through the second pad (PD2), to transmit a first data signal synchronized with the communication control signal (CCTRL) to the slave device (120) and to receive a second data signal synchronized with the communication control signal (CCTRL) from the slave device (120), wherein the first data signal is transmitted to the slave device (120) by the master device (110) in a write mode and the second data signal is received from the slave device (120) in a read mode, characterized in that the communication interface is configured to start the read mode by transiting the communication control signal (CCTRL) from a first voltage level to a second voltage level while the second pad (PD2) has a predetermined voltage level, wherein the communication interface is configured to start the write mode by transiting a voltage of the second pad (PD2) from a first logic level to a second logic level while controlling the communication control signal (CCTRL) to have the first voltage level, and wherein the predetermined voltage level corresponds to the first logic level.
  2. The master device (110) according to claim 1, wherein the communication interface is configured to transmit a plurality of clock pulses (P1 to P11) to the slave device (120) as the communication control signal (CCTRL) after the read mode is started.
  3. The master device (110) according to claim 2, further comprising: a controller (112) to control the communication interface, wherein the communication interface is configured to provide data bits corresponding to the second data signal to the controller (112) in response to a voltage of the second pad (PD2) having a logic high at a time when a last clock pulse of the plurality of clock pulses (P1 to P11) is transmitted.
  4. The master device (110) according to claim 2, wherein the second data signal has a voltage that changes to a first logic level and a second logic level in synchronization with the plurality of clock pulses (P1 to P11), and wherein the predetermined voltage level corresponds to the first logic level.
  5. The master device (110) according to any of claims 1 to 4, wherein the second voltage level is lower than the first voltage level, wherein, in the read mode, after the second data signal is transmitted by the slave device (120), the second pad (PD2) is biased to the predetermined voltage level, and wherein the communication interface is configured to end the read mode by transiting the communication control signal from the second voltage level to the first voltage level while the second pad (PD2) has the predetermined voltage level.
  6. The master device (110) according to claim 1, wherein the communication interface is configured to transmit a plurality of clock pulses (P1 to P11) to the slave device (120) as the communication control signal (CCTRL) after the write mode is started and to transmit the first data signal to the slave device (120) in synchronization with the plurality of clock pulses (P1 to P11).
  7. The master device (110) according to claim 1 or 6, wherein after the first data signal is transmitted to the slave device (120) in the write mode, the communication interface is configured to end the write mode by transiting the voltage of the second pad (PD2) from the second logic level to the first logic level while controlling the communication control signal (CCTRL) to have the first voltage level.
  8. A method of controlling a master device (110) connected to a slave device (120) through a first wire (WR1) and a second wire (WR2) to communicates with the slave device (120), the method comprising: transmitting a read start command to the slave device (120); and receiving a data signal from the slave device (120) through the second wire (WR2) while transmitting a communication control signal (CCTRL) to the first wire (WR1) after the read start command is transmitted, transmitting a write start command to the slave device (120); and transmitting another data signal to the slave device (120) through the second wire (WR2) while transmitting the communication control signal (CCTRL) to the first wire (WR1), after the write start command is transmitted, characterized in that transmitting the read start command comprises outputting the read start command by transiting the communication control signal (CCTRL) from a first voltage level to a second voltage level while the second wire has a predetermined voltage level, and wherein the transmitting the write start command comprises outputting the write start command by transiting a voltage of the second wire (WR2) from a first logic level to a second logic level while controlling the communication control signal (CCTRL) to have the first voltage level.
  9. The method according to claim 8, wherein the receiving the data signal from the slave device (120) comprises transmitting a plurality of clock pulses (P1 to P11) to the slave device (120) as the communication control signal (CCTRL), and wherein the data signal is synchronized with the plurality of clock pulses (P1 to P11).
  10. The method according to claim 8 or 9, further comprising: determining data bits corresponding to the data signal as normal data in response to a voltage of the second wire (WR2) having a logic high at a time when a last clock pulse of the plurality of clock pulses (P1 to P11) is transmitted; and transmitting the read start command to the slave device (120) again in response to a voltage of the second wire (WR2) which does not have a logic high at a time when a last clock pulse of the plurality of clock pulses (P1 to P11) is transmitted.
  11. The method according to claim 9, further comprising: outputting a read end command by transiting the communication control signal from the second voltage level to the first voltage level while the second wire has the predetermined voltage level after the data signal is received from the slave device (120).
  12. A display device (1100, 1200) comprising a master device (110) to communicate with a slave device (120) according to claim 1.
  13. The display device (1100, 1200) according to claim 12, comprising: a display panel (1110, 1210, 1410, 1510); and the master device (110) being a driver integrated circuit (1120, 1420, 1520) connected to the display panel (1110, 1210, 1410, 1510) through a plurality of signal lines to drive the display panel (1110, 1210, 1410, 1510), wherein the driver integrated circuit (1120, 1420, 1520) comprises: a first pad (PD1) and a second pad (PD2) connected to the slave device (120) being a power management integrated circuit (1130, 1230, 1430, 1530) configured to provide a power voltage to at least one of the display panel (1110, 1210, 1410, 1510) and the driver integrated circuit (1120, 1420, 1520).

Description

BACKGROUND 1. Field The disclosure relates to an electronic device, and more particularly, to a master device to communicate with a slave device, the slave device, a method of controlling the same, and a display device including the same. 2. Description of the Related Art A communication system employing serial communication communicates data in a unit of one bit through a communication channel. The serial communication contrasts with parallel communication which communicates data in a unit of multiple bits through multiple parallel channels. A communication system may be designed to interconnect two integrated circuits. The integrated circuit becomes more expensive as the integrated circuit includes more pins. In order to reduce the number of pins, the communication system may employ the serial communication. For example, the communication system may employ serial peripheral interface (SPI) communication, inter-integrated circuit (I2C) communication, or the like. The I2C communication performs communication between a master device and a slave device through a channel including a serial data line (SDA) pulled up by resistors and a serial clock line (SCL). In the I2C communication, the master device requires to preferentially output an address corresponding to the slave device, a type of an operation to be performed (for example, reading or writing) to a channel in order to communicate data (or a command) with the slave device. The US 6 874 047 B1 discloses a system for implementing an SMBus/I2C interface in a networks system for AC-powered computers when such computers execute power management functions, i.e., when such computers are sleeping by extending a low period of a clock signal thereby stretching the clock signal to complete a reading operation. The above-described content is only intended to help understanding of the background of the technical ideas of the disclosure, and thus it cannot be understood as the prior art known to those skilled in the art. SUMMARY An object of the present invention is to provide a master device, a slave device, and a method of controlling the same according to embodiments of the disclosure which may perform reading and writing between the master device and the slave device at an improved speed. The master device includes a first pad, a second pad, and an interface that communicates with the slave device through the first and second pads, and the interface may transmit a command indicating not only a type of an operation to be performed but also one of a start and an end of the corresponding operation type to the slave device, through a combination of a voltage signal of the first pad and a voltage signal of the second pad. In addition, the display device according to embodiments of the disclosure may include the master device and/or the slave device that perform reading and writing between the master device and the slave device at an improved speed. According to the present invention, a master device to communicate with a slave device includes the features of claim 1 of the appended set of claims. The communication interface may be configured to transmit a plurality of clock pulses to the slave device as the communication control signal after the read mode is started. In the read mode, the second data signal transmitted by the slave device may be synchronized with at least some of the plurality of clock pulses. The master device may further include a controller to control the communication interface. The communication interface may be configured to provide data bits corresponding to the second data signal to the controller in response to a voltage of the second pad having a logic high at a time when a last clock pulse of the plurality of clock pulses is transmitted. The first data signal may have a voltage that changes to a first logic level and a second logic level in synchronization with the plurality of clock pulses, and the predetermined voltage level may correspond to the first logic level. The second voltage level may be lower than the first voltage level. In the read mode, after the second data signal is transmitted by the slave device, the second pad may be biased to the predetermined voltage level. The communication interface may be configured to end the read mode by transiting the communication control signal from the second voltage level to the first voltage level while the second pad has the predetermined voltage level. The communication interface is configured to start the write mode by transiting a voltage of the second pad from a first logic level to a second logic level while controlling the communication control signal to have the first voltage level. The predetermined voltage level corresponds to the first logic level. The communication interface may be configured to transmit a plurality of clock pulses to the slave device as the communication control signal after the write mode is started, and to transmit the first data signal to the slave device in