EP-4425368-B1 - CHIP INTERNAL VOLTAGE PREDICTION MODEL GENERATION METHOD, CHIP INTERNAL VOLTAGE PREDICTION METHOD, AND RELATED APPARATUSES

EP4425368B1EP 4425368 B1EP4425368 B1EP 4425368B1EP-4425368-B1

Inventors

DAI, Kaiyong
YANG, YI
FU, Xingfei
PAN, YU

Dates

Publication Date: 20260506
Application Date: 20230914

Claims (13)

A generation method for a chip internal voltage prediction model, comprising: obtaining (S110) a load data set and a relevant index data set of a chip respectively, wherein the load data set comprises load data of the chip at each sampling cycle and a sampling cycle ordinal number corresponding to the load data, and the relevant index data set comprises characterization data characterizing a chip internal voltage at the each sampling cycle and a sampling cycle ordinal number corresponding to the characterization data; calibrating (S120) the relevant index data set according to a calibration cycle number and obtaining a calibrated relevant index data set; and training (S130) the chip internal voltage prediction model based on the load data set and the calibrated relevant index data set, and obtaining the chip internal voltage prediction model with completed training.
The generation method for the chip internal voltage prediction model according to claim 1, wherein the load data comprises instruction data and/or cache data, the instruction data is a number of each type of instructions in an instruction life cycle of the chip, and the cache data is a number of reads and writes in progress in a cache of the chip.
The generation method for the chip internal voltage prediction model according to claim 1 or 2, wherein the characterization data is power monitoring data and/or power consumption data.
The generation method for the chip internal voltage prediction model according to any one of claims 1-3, wherein in calibrating the relevant index data set according to the calibration cycle number and obtaining the calibrated relevant index data set, a calculation method for the calibration cycle number comprises: recording (S121) a sampling cycle ordinal number T1 corresponding to the load data reaching a maximum value of the load data, and a sampling cycle ordinal number T2 corresponding to the characterization data reaching a maximum value of the characterization data, in a process of gradually increasing a computational load of the chip to a maximum value and maintaining a state of the maximum value; and taking a difference (S122) between the sampling cycle ordinal number T1 corresponding to the load data reaching the maximum value of the load data and the sampling cycle ordinal number T2 corresponding to the characterization data reaching the maximum value of the characterization data as the calibration cycle number.
The generation method for the chip internal voltage prediction model according to any one of claims 1-4, wherein calibrating the relevant index data set according to the calibration cycle number comprises: reducing the sampling cycle ordinal number corresponding to the characterization data in the relevant index data set by the calibration cycle number.
The generation method for the chip internal voltage prediction model according to any one of claims 1-5, wherein the sampling cycle is a clock cycle of the chip.
A generation apparatus for the chip internal voltage prediction model, comprising: an obtaining module (110), configured to obtain a load data set and a relevant index data set of a chip respectively, wherein the load data set comprises load data of the chip at each sampling cycle and a sampling cycle ordinal number corresponding to the load data, and the relevant index data set comprises characterization data characterizing a chip internal voltage at the each sampling cycle and a sampling cycle ordinal number corresponding to the characterization data; a calibration module (120), configured to calibrate the relevant index data set according to a calibration cycle number and obtain a calibrated relevant index data set; and a training module (130), configured to train the chip internal voltage prediction model based on the load data set and the calibrated relevant index data set and obtain the chip internal voltage prediction model with completed training.
A prediction method for a chip internal voltage, comprising: obtaining (S310) real-time load data of a chip; and obtaining (S320) prediction data of the chip internal voltage using a chip internal voltage prediction model obtained by the generation method for the chip internal voltage prediction model according to any one of claims 1-6.
The prediction method for the chip internal voltage according to claim 8, wherein the real-time load data comprises instruction data and/or cache data, the instruction data is a number of each type of instructions in an instruction life cycle of the chip, and the cache data is a number of reads and writes in progress in a cache of the chip.
A prediction apparatus for a chip internal voltage, comprising: a real-time obtaining module (310), configured to obtain real-time load data of a chip; and a prediction module (320), configured to obtain prediction data of the chip internal voltage using a chip internal voltage prediction model obtained by the generation method for the chip internal voltage prediction model according to any one of claims 1-6.
A storage medium, wherein the storage medium stores a program adapted for generation of a chip internal voltage prediction model so as to implement the generation method for the chip internal voltage prediction model according to any one of claims 1-6, or the storage medium stores a program adapted for prediction of a chip internal voltage so as to implement the prediction method for the chip internal voltage according to claim 8 or 9.
An electronic device, comprising at least one memory and at least one processor, wherein the memory stores a program, and the processor invokes the program to perform the generation method for the chip internal voltage prediction model according to any one of claims 1-6, or to perform the prediction method for the chip internal voltage according to claim 8 or 9.
A chip, comprising: an instruction counting unit, configured to obtain a number of each type of instructions in an instruction life cycle of the chip; a cache access counting unit, configured to obtain a number of reads and writes in progress in a cache of the chip; and a prediction unit, configured to obtain, using a chip internal voltage prediction model obtained by the generation method for the chip internal voltage prediction model according to any one of claims 1-6, prediction data of a chip internal voltage according to the number of each type of instructions obtained by the instruction counting unit and the number of reads and writes obtained by the cache access counting unit.

Description

The present application claims the priority to the Chinese Patent Application No. 202211647622.4 filed on December 21, 2022. TECHNICAL FIELD Embodiments of the present disclosure relate to a generation method for a chip internal voltage prediction model, a prediction method, and related apparatuses. BACKGROUND The system-level chip, also referred to as system-on-a-chip (SOC), is an integrated circuit with a dedicated target. The power supply system of the system-level chip includes: a power supply, a power line, an internal power network, and the like. The internal device of the system-level chip is connected to the internal power network, and the internal power network is connected to the power supply through the power line. During operation of the system-level chip, the power line between the internal power network and the power supply may generate a current. Meanwhile, because of the existence of the internal resistance of the power supply and the internal resistance of the internal power network, there is a voltage drop from the power supply to the internal power network, and further because the internal device is connected to the internal power network, it can be assumed that the voltage drop is a voltage decrease from the power supply to the internal device of the chip. However, when the load of the chip is suddenly increased, the rate of change of the current with time (also referred to as DIDT) suddenly increases. In the case of a short period of time when the voltage value of the power supply remains unchanged, the voltage drop from the power supply to the internal device of the chip will become larger, and the voltage on the internal device will drop sharply, which may cause the functional failure of the entire system-level chip. One solution to the above problem is to detect DIDT-related data in the chip in real time in order to evaluate whether the chip internal voltage is abnormal, and intervene in the operating status of the chip after determining that the chip internal voltage is abnormal. However, it is usually too late to intervene in the operating status of the chip when the chip internal voltage is determined to be abnormal. Therefore, how to timely detect the abnormal chip internal voltage caused by the DIDT has become an urgent technical problem for those skilled in the art to solve YE FANGMING ET AL: "On-chip voltage-droop prediction using support-vector machines", 2014 IEEE 32ND VLSI TEST SYMPOSIUM describes on-chip voltage droop prediction using support-vector machines. SUMMARY In view of this, the embodiments of the present disclosure provide a generation method for a chip internal voltage prediction model, a prediction method, and related apparatuses, which can predict the chip internal voltage in advance. To achieve the above-mentioned purpose, the embodiments of the present disclosure provide the following technical solutions. In a first aspect, the embodiments of the present disclosure provide a generation method for a chip internal voltage prediction model, which includes: obtaining a load data set and a relevant index data set of a chip respectively, where the load data set includes load data of the chip at each sampling cycle and a sampling cycle ordinal number corresponding to the load data, and the relevant index data set includes characterization data characterizing a chip internal voltage at the each sampling cycle and a sampling cycle ordinal number corresponding to the characterization data;calibrating the relevant index data set according to a calibration cycle number and obtaining a calibrated relevant index data set; andtraining the chip internal voltage prediction model based on the load data set and the calibrated relevant index data set, and obtaining the chip internal voltage prediction model with completed training. In a second aspect, the embodiments of the present disclosure further provide a generation apparatus for a chip internal voltage prediction model, which includes: an obtaining module, configured to obtain a load data set and a relevant index data set of a chip respectively, where the load data set includes load data of the chip at each sampling cycle and a sampling cycle ordinal number corresponding to the load data, and the relevant index data set includes characterization data characterizing a chip internal voltage at the each sampling cycle and a sampling cycle ordinal number corresponding to the characterization data;a calibration module, configured to calibrate the relevant index data set according to a calibration cycle number and obtain a calibrated relevant index data set; anda training module, configured to train the chip internal voltage prediction model based on the load data set and the calibrated relevant index data set and obtain the chip internal voltage prediction model with completed training. In a third aspect, the embodiments of the present disclosure further provide a prediction method for a chip internal voltage, which includes: