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EP-4428927-B1 - MULTI-CHANNEL HIGH ELECTRON MOBILITY TRANSISTOR WITH REDUCED INPUT CAPACITANCE

EP4428927B1EP 4428927 B1EP4428927 B1EP 4428927B1EP-4428927-B1

Inventors

  • OSTERMAIER, CLEMENS

Dates

Publication Date
20260506
Application Date
20240216

Claims (11)

  1. A high-electron mobility transistor (100), comprising: a semiconductor body (102) comprising a plurality of type III-nitride semiconductor layers (106,108) stacked on top of one another, thereby forming a plurality of two-dimensional first charge type gas channels (110) and at least one two-dimensional second charge type gas channel (112) vertically in between two of the two-dimensional first charge type gas channels (110), source (116) and drain (118) electrodes that are laterally spaced apart from one another; a gate structure (120) configured to control a conductive connection between the source (116) and drain (118) electrodes by controlling a conductive state of the plurality of two-dimensional first charge type gas channels (110); and a charge dissipation structure (124) that is configured to remove second charge type carriers from the at least one two-dimensional second charge type gas channel (112) during an off-state of the high-electron mobility transistor (100), wherein the charge dissipation structure (124) comprises one or more regions of second conductivity type semiconductor material extending through the plurality of type III-nitride semiconductor layers (106,108) and directly interfacing with the at least one two-dimensional second charge type gas channel (112) characterised in that ; the source (116) and the drain (1118) are in ohmic contact with the plurality of two-dimensional first charge type gas channels (110); a barrier structure (128) is laterally in between the gate structure (120) and an access region (132) of the high-electron mobility transistor (100), wherein the barrier structure (128) forms an energy barrier that prevents second charge type carriers from flowing between the access region (132) of the high-electron mobility transistor (100) and the gate structure (120), wherein the barrier structure (128) is a region of first conductivity type semiconductor material that extends through the plurality of type III-nitride semiconductor layers (106,108) and separates the access region of the high-electron mobility transistor (100) from the gate structure (120).
  2. The high-electron mobility transistor (100) of claim 1, wherein the charge dissipation structure (124) and the source electrode (116) are connected to the same potential.
  3. The high-electron mobility transistor (100) of any one of claims 1 to 2, wherein the gate structure (120) comprises a plurality of gate columns (122), and wherein each of the gate columns (122) is a region of second conductivity type semiconductor material that extends through the plurality of type III-nitride semiconductor layers (106,108) and directly interfaces with the at least one two-dimensional second charge type gas channel (112).
  4. The high-electron mobility transistor of any one of claims 1 to 3, wherein the charge dissipation structure (124) is disposed within the access region (132).
  5. The high-electron mobility transistor (100) of any one of claims 1 to 4, wherein the charge dissipation structure (124) comprises a plurality of charge dissipation columns (126), wherein each of the charge dissipation columns (126) is a region of second conductivity type semiconductor material that extends through the plurality of type III-nitride semiconductor layers (106,108) and directly interfaces with the at least one two-dimensional second charge type gas channel (112).
  6. The high-electron mobility transistor according to claim 5, wherein the charge dissipation columns (126) and the gate columns (122) differ from one another with respect to at least one of the following parameters: dopant concentration, and lateral spacing in a second direction that is perpendicular to a current flow direction of the high-electron mobility transistor (100).
  7. The high-electron mobility transistor (100) of any one of claims 1 to 6, wherein the charge dissipation structure (124) is at least partially overlapping with the source electrode (116).
  8. The high-electron mobility transistor (100) according to claim 7, wherein the one or more regions of second conductivity type semiconductor material of the charge dissipation structure (124) extend past the gate structure (120) and towards the drain electrode (118).
  9. A method forming a high-electron mobility transistor (100), the method comprising: providing a semiconductor body (102) comprising a plurality of type III-nitride semiconductor layers (106,108) stacked on top of one another, thereby forming a plurality of two-dimensional first charge type gas channels (110) and at least one two-dimensional second charge type gas channel (112) vertically in between two of the two-dimensional first charge type gas channels (110), forming source (116) and drain (118) electrodes that are laterally spaced apart from one another; forming a gate structure (120) that is configured to control a conductive connection between the source (116) and drain (118) electrodes by controlling a conductive state of the plurality of two-dimensional first charge type gas channels (110); and forming a charge dissipation structure (124) that is configured to remove second charge type carriers from the two-dimensional second charge type gas channel (112) during an off-state of the high-electron mobility transistor (100), wherein forming the charge dissipation structure (124) comprises forming one or more regions of second conductivity type semiconductor material that extend through the plurality of type III-nitride semiconductor layers (106,108) and directly interface with the at least one two-dimensional second charge type gas channel (112). characterised by ; forming the source (116) and drain (118) electrodes to be in ohmic contact with the plurality of two-dimensional first charge type gas channels (110); forming a barrier structure (128) laterally in between the gate structure (120) and an access region (132) of the high-electron mobility transistor (100), wherein the barrier structure (128) forms an energy barrier that prevents second charge type carriers from flowing between the access region (132) of the high-electron mobility transistor (100) and the gate structure (120), wherein the barrier structure (128) is a region of first conductivity type semiconductor material that extends through the plurality of type III-nitride semiconductor layers (106,108) and separates the access region (132) of the high-electron mobility transistor (100) from the gate structure (120).
  10. The method of claim 9, wherein the gate structure (120) comprises a plurality of gate columns (122), and wherein each of the gate columns (122) is a region of second conductivity type semiconductor material that extends through the plurality of type III-nitride semiconductor layers (106,108) and directly interfaces with the at least one two-dimensional second charge type gas channel (112).
  11. The method of claim 9 or 10, wherein the charge dissipation structure (124) is disposed within an access region (132) of the high electron mobility transistor (100), wherein the charge dissipation structure (124) comprises a plurality of charge dissipation columns (126), and wherein each of the charge dissipation columns (126) is a region of second conductivity type semiconductor material that extends through the plurality of type III-nitride semiconductor layers (106,108) and directly interfaces with the at least one two-dimensional second charge type gas channel (112).

Description

BACKGROUND HEMTs (high-electron-mobility Field Effect Transistors) also known as heterostructure FETs (HFETs) and modulation-doped FET (MODFETs) offer high conduction and low losses in comparison to many conventional semiconductor transistor designs. These advantageous conduction characteristics make HEMTs desirable in applications including, but not limited to, use as switches in power supplies and power converters, electric cars, air-conditioners, and in consumer electronics, for example. Designers are constantly seeking ways to improve the performance of HEMTs, e.g., power consumption and voltage blocking capability. Exemplary device parameters that designers seek to improve include leakage current, threshold voltage (VTH), drain-source on-state resistance (RDSON), and maximum voltage switching capability, to name a few. Multi-channel HEMTs that utilize more than one device channel are currently under investigation. This device concept advantageously lowers the on-resistance of the device by including multiple conduction paths in parallel between the source and drain of the device. Current multi-channel HEMT designs involve making unwanted tradeoffs between drain-source on-state resistance (RDSON) and input capacitance. US 2016/247905A1 discloses a Group III-nitride-based enhancement mode transistor which includes a multi-heterojunction fin structure. A first side face of the multi-heterojunction fin structure is covered by a first p-type Group III-nitride layer, and a second side face of the multi-heterojunction fin structure is covered by a second p-type Group III-nitride layer. US2015221748A1 discloses a method of manufacturing a transistor device which includes forming a semiconductor heterostructure including a plurality of alternating two-dimensional electron gasses (2DEGs) and two-dimensional hole gasses (2DHGs) extending in parallel at different depths in the semiconductor heterostructure. The 2DEGs form current channels of the transistor device, forming a source extending into the semiconductor heterostructure in contact with the 2DEGs at a first end of the current channels, forming a drain extending into the semiconductor heterostructure in contact with the 2DEGs at an opposing second end of the current channels, and forming a plurality of spaced apart gate structures extending into the semiconductor heterostructure and including an electrically conductive material separated from the surrounding semiconductor heterostructure by an insulating material. US2018219086A1 discloses a nitride semiconductor device which includes a horizontal switching device that includes a substrate, a channel forming layer, a source region, a drain region and a gate region. The source region and the drain region are arranged apart from each other in one direction along a plane of the substrate. The gate region is formed of a p-type semiconductor layer and is arranged between the source region and the drain region. The gate region is divided into multiple parts in a perpendicular direction along the plane of the substrate, the perpendicular direction being perpendicular to an arrangement direction in which the source region and the drain region are arranged. US10128228B1 discloses a semiconductor device which includes a type IV semiconductor base substrate, a first type III-V semiconductor layer formed over the base substrate, a second type III-V semiconductor layer formed over the first type III-V semiconductor layer. A two-dimensional charge carrier gas forms at an interface between the first and second type III-V semiconductor layers. First and second electrically conductive device terminals are in ohmic contact with the two-dimensional charge carrier gas. A gate electrode is formed on the first type III-V semiconductor layer and is configured to control a conduction state of the two-dimensional charge carrier gas. An electrically insulating region is disposed over the second type III-V semiconductor layer and is laterally between the gate electrode and the second electrically conductive device terminal. At least one diode is formed on the electrically insulating region and is electrically connected between the gate electrode and the second electrically conductive device terminal. SUMMARY A high-electron mobility transistor is disclosed. According to the invention, the high-electron mobility transistor comprises a semiconductor body comprising a plurality of type III-nitride semiconductor layers stacked on top of one another, thereby forming a plurality of two-dimensional first charge type gas channels and at least one two-dimensional second charge type gas channel vertically in between two of the two-dimensional first charge type gas channels, source and drain electrodes that are laterally spaced apart from one another and in ohmic contact with the plurality of two-dimensional first charge type gas channel, a gate structure configured to control a conductive connection between the source and drain electrodes by co