EP-4433932-B1 - METHOD FOR A SECURE EXECUTION OF A HARDWARE INSTRUCTION

Inventors

• TEGLIA, YANNICK
• Sintzoff, André
• Coulon, Jean Roch

Dates

Publication Date

20260506

Application Date

20221117

Claims (13)

1. A method for a secure execution of a first instruction by processing means (101) of an electronic system (100), comprising: - fetching (S1) said first instruction in an execution pipeline of the processing means, - determining (S2) that said first instruction to be executed is an instruction sensitive to a determined attack, wherein said first instruction, when executed by the processing means, causes the processing means to perform a first function, - selecting (S3), based on said determined attack, from an internal memory (102a, 102b) of said processing means, at least one second instruction, which, when executed by the processing means, causes the processing means to perform a combination of said first function and a dedicated security countermeasure against said determined attack, - executing (S4) said selected at least one second instruction instead of said first instruction.
2. The method of claim 1, wherein, said dedicated security counter measure is among variable bounding check, multi memory access and execution desynchronization.
3. The method of claim 2, wherein, said dedicated security countermeasure is a variable bounding check to verify that a value to be loaded is between a minimum value and a maximal value and said selected second instructions comprise hardware instructions which, when executed by the processing means, cause the processing means to load said value to be loaded, said minimum value and said maximum value, to compare said value to be loaded to said minimum value, to compare said value to be loaded to said maximum value and, based on said comparison, to trigger an alarm or not.
4. The method of claim 2, wherein, said dedicated security countermeasure is a multi memory access to verify a value to be loaded and said selected second instructions comprise hardware instructions which, when executed by the processing means, cause the processing means to load twice said value to be loaded, to compare said loaded values and, based on said comparison, to trigger an alarm or not.
5. The method of any one of claims 1 to 4, wherein said selected second instructions address at least one processor register to store temporary values, wherein said processor register cannot be addressed by any instruction of the Instruction Set Architecture of the processing means.
6. The method of any one of claims 1 to 5, wherein selecting (S3) at least one second instruction is based on a predefined policy.
7. The method of any one of claims 1 to 5, wherein selecting (S3) at least one second instruction comprises randomly or pseudo randomly selecting at least one instruction from a plurality of hardware instructions which, when executed by the processing means, cause the processing means to perform said combination of said first function and said dedicated security countermeasure.
8. The method of any one of claims 1 to 7, wherein determining (S2) that said first instruction to be executed is an instruction sensitive to a determined attack comprises detecting in said first instruction a predetermined combination of instruction fields.
9. The method of any one of claims 1 to 8, wherein determining (S2) that said first instruction to be executed is an instruction sensitive to a determined attack comprises detecting a predetermined value of a Program Counter of said processing means.
10. The method of any one of claims 1 to 9, wherein determining (S2) that said first instruction to be executed is an instruction sensitive to a determined attack comprises determining a predetermined indication in a software code ordering an execution of said first instruction.
11. The method of claim 10, wherein determining (S2) that said first instruction to be executed is an instruction sensitive to a determined attack comprises determining a value of at least one predetermined selection bit of said first instruction.
12. A computer program product directly loadable into the memory of at least one computer, comprising software code instructions for performing the steps of any one of claims 1 to 11 when said product is run on the computer.
13. An electronic system (100) comprising processing means (101) configured for performing the steps of any one of claims 1 to 11.

Description

FIELD OF THE INVENTION The present invention relates to the field of securing software execution on an electronic device against attacks, and more particularly to a method for securing the execution of instructions by processing means of the electronic device. BACKGROUND OF THE INVENTION Information about modern CPU (central processing unit) architecture and behavior are more easily accessible nowadays than in the past, either by reverse engineering or through open hardware/open source projects openly disclosing information Such information can be used by an attacker to design efficient attacks using fault injection or side-channel analysis, which would enable the attacker to gain knowledge of sensitive information processed by the CPU such as encryption keys. Countermeasures have been designed against such kind of attacks but they usually have a noticeable impact on performance, particularly by inducing a significant increase of memory accesses. Consequently, there is a need for a method enabling a secure execution of an instruction by a CPU, protected against fault attacks or side-channel analysis, and having a lower impact on performance than existing countermeasures. Documents Nicolas Belleville et al: "Automated Software Protection for the Masses Against Side-Channel Attacks", ACM Transactions on Architecture and Code Optimization (TACO), Volume 15, Issue 4, 2018; Mohammadkazem Taram et al: "Context-Sensitive Fencing: Securing Speculative Execution via Microcode Customization", in Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019; and patent application US2020/159888A1 constitute relevant prior art. SUMMARY OF THE INVENTION For this purpose and according to a first aspect, this invention therefore relates to a method for a secure execution of a first instruction by processing means of an electronic system, comprising: fetching said first instruction in an execution pipeline of the processing means,determining that said first instruction to be executed is an instruction sensitive to a determined attack, wherein said first instruction, when executed by the processing means, causes the processing means to perform a first function,selecting, based on said determined attack, from an internal memory of said processing means, at least one second instruction, which, when executed by the processing means, causes the processing means to perform a combination of said first function and a dedicated security countermeasure against said determined attack,executing said selected second instructions instead of said first instruction. Such a method enables to add countermeasures to the execution of the instructions performing the first function. Since the replacement of instructions is performed by the processing means themselves directly from an internal memory, it does not require any additional fetching or loading from the main memory of the electronic system, which lowers the impact on performances. Said dedicated security counter measure may be among variable bounding check, multi memory access, and execution desynchronization. According to a first embodiment, said dedicated security countermeasure is a variable bounding check to verify that a value to be loaded is between a minimum value and a maximal value and said selected second instructions comprise hardware instructions which, when executed by the processing means, cause the processing means to load said value to be loaded, said minimum value and said maximum value, to compare said value to be loaded to said minimum value, to compare said value to be loaded to said maximum value and, based on said comparison, to trigger an alarm or not. It enables to prevent fault attacks or malicious software from modifying a value to be loaded out of its allowed range. According to a second embodiment, said dedicated security countermeasure is a multi memory access to verify a value to be loaded and said selected second instructions comprise hardware instructions which, when executed by the processing means, cause the processing means to load twice said value to be loaded, to compare said loaded values and, based on said comparison, to trigger an alarm or not. It enables to prevent fault attacks modifying the value to be loaded after the first loading of the value. Said selected second instructions may address at least one processor register to store temporary values, and said processor register cannot be addressed by any instruction of the Instruction Set Architecture of said processing means. Selecting at least one second instruction may be based on a predefined policy. Selecting at least one second instruction may comprise randomly or pseudo randomly selecting at least one instruction from a plurality of hardware instructions which, when executed by the processing means, cause the processing means to perform said combination of said first function and said dedicated security counterme