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EP-4435553-B1 - LOW DROPOUT REGULATOR

EP4435553B1EP 4435553 B1EP4435553 B1EP 4435553B1EP-4435553-B1

Inventors

  • XIE, Can
  • LIU, ZHI

Dates

Publication Date
20260506
Application Date
20231221

Claims (7)

  1. A low dropout regulator comprising: an error amplifier (EA), comprising a second current mirror (P3/P5), a pair of differential input transistors (P6, P7) and loads (N6/N5, N7/N8) respectively coupled to the pair of differential input transistors (P6, P7), wherein, a gate of a first input transistor (P6) in the pair (P6, P7) receives a reference voltage (VREF) and a gate of a second input transistor (P7) in the pair (P6, P7) receives an output voltage (VOUT) of the low dropout regulator or a sampled voltage (VS) obtained by sampling the output voltage (VOUT); wherein, the load (N6/N5) coupled to the first input transistor (P6) comprises a third current mirror (N6/N5) complementary to the type of the first input transistor (P6), and the load (N7/N8) coupled to the second input transistor (P7) comprises a fourth current mirror (N7/N8) complementary to the type of the second input transistor (P7), the reference branch (P3) of the second current mirror (P3/P5) is coupled to the output branch (N5) of the third current mirror (N6/N5), the output branch (P5) of the second current mirror (P3/P5) and the output branch (N8) of the fourth current mirror (N7/N8) are coupled at a node which is an output terminal (VO1) of the error amplifier (EA); a power transistor (MP), the gate of which is coupled to the output terminal (VO1) of the error amplifier (EA), and the drain of which serves as an output node to output the output voltage (VOUT); a first frequency compensation branch (201), comprising a first frequency compensation capacitor (C CA1 ) and a current amplifier (CA) for amplifying the current flowing through the first frequency compensation capacitor (C CA1 ), wherein, the current amplifier (CA) comprises a current source (N4+N1;N9; Ib) and a first current mirror (P1/P2) with a current amplification factor (B1) greater than 1, the current source (N4+N1;N9; Ib) is coupled to the reference branch (P1) of the first current mirror (P1/P2), one end of the first frequency compensation capacitor (C CA1 ) is coupled to the output node, and the other end is coupled to a node within the current source (N4+N1; Ib), or is coupled to a node at which the reference branch (P1) of the first current mirror (P1/P2) and the current source (N4+N1;N9; Ib) are coupled, and the drain of the output transistor (P2) of the first current mirror (P1/P2) is coupled to the drain of the reference transistor (P3) of the second current mirror (P3/P5), so that the first frequency compensation capacitor (C CA1 ), together with at least the first current mirror (P1/P2), the second current mirror (P3/P5), and the power transistor (MP), forms a first negative feedback loop in the low dropout regulator; and a second frequency compensation capacitor (C CA2 ), coupled between a second internal node of the error amplifier (EA) and the output node, so as to form a left half-plane zero of the low dropout regulator; wherein, the second internal node is a node at which the first input transistor (P6) and its load (N6/N5) are coupled.
  2. The low dropout regulator according to claim 1, wherein, the third current mirror (N6/N5) and the second current mirror (P3/P5) both have current amplification factors (B3, B2) greater than 1.
  3. The low dropout regulator according to claim 1, wherein, the current source (N4+N1;N9; Ib) to which the reference branch (P1) of the first current mirror (P1/P2) is coupled includes two cascoded transistors (N4+N1) for generating a reference current, and the first frequency compensation capacitor (C CA1 ) is coupled to a node at which the cascoded transistors (N4+N1) are connected.
  4. The low dropout regulator according to claim 1, wherein, the zero formed by the second frequency compensation capacitor (C CA2 ) is fixed.
  5. The low dropout regulator according to claim 1, wherein, the first input transistor (P6) and the second input transistor (P7) are PMOS transistors, the third current mirror (N6/N5) and the fourth current mirror (N7/N8) are NMOS current mirrors, the second current mirror (P3/P5) and the first current mirror (P1/P2) are PMOS current mirrors, the current source (N4+N1; N9; Ib) to which the reference branch (P1) of the first current mirror (P1/P2) is coupled includes two cascoded NMOS transistors (N4+N1) for generating a reference current, and the first frequency compensation capacitor (C CA1 ) is coupled to a node at which the cascoded NMOS transistors (N4+N1) are connected.
  6. The low dropout regulator according to claim 1, wherein, the third current mirror (N6/N5) and the second current mirror (P3/P5) both have a current amplification factor (B3, B2) greater than 1, and the current flowing through the second frequency compensation capacitor (C CA2 ) is amplified by at least the third current mirror (N6/N5), the second current mirror (P3/P5) and the power transistor (MP), so that the second frequency compensation capacitor (C CA2 ), together with at least the third current mirror (N6/N5), the second current mirror (P3/P5) and the power transistor (MP), forms a second negative feedback loop in the low dropout regulator.
  7. The low dropout regulator according to claim 1, wherein, the output node is coupled to an off-chip load capacitor (CL), the capacitance value of the off-chip load capacitor (CL) is of a magnitude level of µF, and the capacitance values of the first and second frequency compensation capacitors (C CA1 , C CA2 ) are of a magnitude level of pF; and/or the equivalent capacitance of the output terminal (VO1) of the error amplifier (EA) is of a magnitude level of pF.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to Chinese patent application No. 202310280313.6 filed on March 21, 2023. TECHNICAL FIELD The disclosure herein relates to the field of analog circuits, and in particular to a low dropout regulator. BACKGROUND A low dropout regulator (LDO) is usually used to reduce an external power supply voltage by a certain value and stably output the reduced voltage as a power supply voltage required by some circuits. Usually, LDO is a feedback system, which needs frequency compensation to ensure the stability of the system. However, since the load current of the LDO will vary greatly in practical applications, which will result in the transconductance and output impedance of its output power transistor to vary greatly, a large change in the related poles may be caused, which poses a challenge for the stability of the LDO. In the existing circuit design of the LDO, a voltage buffer is usually inserted between the output of the error amplifier (EA) and the gate of the power transistor to solve the stability problem. However, the introduction of the voltage buffer will reduce the swing of the gate of the power transistor and increase the requirement on the power supply voltage, so this structure is no longer applicable in the case of low power supply voltage and high load current. Therefore, there is a need for a highly stable LDO circuit design suitable for low power supply voltage and wide load current range. Various schemes have been proposed for a highly stable LDO circuit design. US10768650B1 discloses a voltage regulator including a frequency compensation circuit having a first capacitor coupled to a capacitance multiplier which has a second capacitor coupled to a voltage amplifier. US2012/280667A1 describes an LDO regulator comprising a first output current feedback loop, aiming to reducing the size or capacitance of a bypass capacitor. SUMMARY One of the technical problems to be solved by the present disclosure is to provide an LDO with high stability, suitable for low power supply voltage and wide load current range. The invention is defined as set out in the independent claim 1. Further embodiments are depicted in the dependent claims. According to a first aspect of the invention, a low dropout regulator is provided, which comprises: an error amplifier, comprising a second current mirror, a pair of differential input transistors and loads respectively coupled to the pair of differential input transistors, wherein, a gate of a first input transistor in the pair receives a reference voltage and a gate of a second input transistor in the pair receives an output voltage of the low dropout regulator or a sampled voltage obtained by sampling the output voltage; wherein, the load coupled to the first input transistor comprises a third current mirror complementary to the type of the first input transistor, and the load coupled to the second input transistor comprises a fourth current mirror complementary to the type of the second input transistor, the reference branch of the second current mirror is coupled to the output branch of the third current mirror, the output branch of the second current mirror and the output branch of the fourth current mirror are coupled at a node which is an output terminal of the error amplifier; a power transistor, the gate of which is coupled to the output terminal of the error amplifier, and the drain of which serves as an output node to output the output voltage; a first frequency compensation branch, comprising a first frequency compensation capacitor and a current amplifier for amplifying the current flowing through the first frequency compensation capacitor, wherein, the current amplifier comprises a current source and a first current mirror with a current amplification factor greater than 1, the current source is coupled to the reference branch of the first current mirror, one end of the first frequency compensation capacitor is coupled to the output node, and the other end is coupled to a node within the current source, or is coupled to a node at which the reference branch of the first current mirror and the current source are coupled, and the drain of the output transistor of the first current mirror is coupled to the drain of the reference transistor of the second current mirror, so that the first frequency compensation capacitor, together with at least the first current mirror, the second current mirror, and the power transistor, forms a first negative feedback loop in the low dropout regulator; and a second frequency compensation capacitor, coupled between a second internal node of the error amplifier and the output node, so as to form a left half-plane zero of the low dropout regulator; wherein, the second internal node is a node at which the first input transistor and its load are coupled. Optionally, the third current mirror and the second current mirror both have current amplification factors greater th