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EP-4435786-B1 - MEMORY WITH ONE-TIME PROGRAMMABLE (OTP) CELLS

EP4435786B1EP 4435786 B1EP4435786 B1EP 4435786B1EP-4435786-B1

Inventors

  • ROY, ANIRBAN
  • MAHATME, NIHAAR N.
  • Choy, Jon Scott

Dates

Publication Date
20260506
Application Date
20240319

Claims (8)

  1. A magnetoresistive random access memory, MRAM, (100) comprising: an MRAM array (102) including MRAM cells (111, 123) arranged in rows and columns, each MRAM cell (111, 123) of the MRAM array including a corresponding Magnetic Tunnel Junction, MTJ, which includes a corresponding tunnel dielectric layer, wherein the corresponding MTJ is capable of being in a blown state or non-blown state, in which, in the non-blown state, the corresponding MTJ is capable of being in a high resistive state, HRS, or a low resistive state, LRS, the LRS corresponding to a lower resistance than the HRS, and the blown state corresponding to a permanent breakdown of the corresponding tunnel dielectric layer which results in a lower resistance than the LRS; write circuitry (103)configured to perform a one-time-programmable, OTP, write operation to blow selected MRAM cells (111, 123) of the MRAM array, characterised in that , for each MRAM cell (111, 123) being blown, the write circuitry is configured to: use an initial OTP program reference for the MRAM cell (111, 123) being blown to detect onset of tunnel dielectric breakdown after application of each OTP write pulse of the OTP write operation; and after detection of the onset, update the initial OTP program reference to obtain an updated OTP program reference, apply at least one additional OTP write pulse to the MRAM cell (111, 123) being blown, and use the updated OTP program reference to verify that current saturation of the MRAM cell (111, 123) being blown has occurred; wherein the initial OTP program reference corresponds to an initial reference current and the updated OTP program reference corresponds to an updated reference current, wherein the write circuitry is configured to, after the application of each OTP write pulse to the MRAM cell (111, 123) being blown, sense a cell current of the MRAM cell (111, 123) being blown as compared to the initial reference current; wherein the write circuitry is configured to detect the onset of tunnel dielectric breakdown when the sensed cell current is no longer less than the initial reference current; wherein updating the initial OTP program reference comprises incrementally increasing the initial reference current to obtain the updated reference current; wherein the write circuitry is configured to, after incrementally increasing the initial reference current: again sense the cell current of the MRAM cell (111,123) being blown and compare the again sensed cell current with the updated reference current; and apply the at least one additional OTP write pulse when the again sensed cell current is not greater than the updated reference current.
  2. The MRAM (100) of claim 1, wherein the write circuitry is configured to, after again sensing the cell current of the MRAM cell (111,123) being blown: when the again sensed cell current is greater than the updated reference current, incrementally increase the updated reference current, wherein using the updated OTP program reference to verify the current saturation is performed by using the incrementally increased updated reference current to verify the current saturation.
  3. The MRAM (100) of any preceding claim, wherein the write circuitry is configured to use the updated OTP program reference to verify that current saturation of the MRAM cell being blown has occurred by: after applying the at least one additional OTP pulse, again sensing the cell current of the MRAM cell (111,123) being blown and comparing the again sensed cell current with the updated reference current.
  4. The MRAM (100) of claim 3, wherein the write circuitry is configured to verify that the current saturation has occurred when the again sensed cell current remains less than the updated reference current.
  5. The MRAM (100) of any preceding claim, further comprising a control circuit, wherein the initial OTP program reference for the MRAM cell (111, 123) being blown is obtained using one or more values stored in storage circuitry of the control circuit.
  6. The MRAM of claim 5, wherein: the control circuitry is configured to initialize each non-blown MRAM cell (111, 123) of the MRAM array (102) by: directing the write circuitry to program the non-blown MRAM cell (111, 123) to the LRS; setting a read reference current to an initial read reference current; iteratively reading the non-blown cell and incrementally increasing the read reference current until a read current of the non-blown MRAM cell is no longer greater than the read reference current; and after the iteratively reading and incrementally increasing, storing a final value of the read reference current corresponding to the non-blown MRAM cell in the storage circuitry, wherein the write circuitry is configured to obtain the final value of the read reference current from the storage circuitry for the MRAM cell being blown and set the initial OTP program reference based on the obtained final value of the read reference current.
  7. The MRAM (100) of claim 6, further comprising reference circuitry having a reference MRAM cell and configured to receive an OTP reference voltage and generate the read reference current based on the OTP reference voltage.
  8. The MRAM (100) of claim 7, further comprising: a digital to analog converter, DAC (244) configured to output the OTP reference voltage to the reference MRAM cell, wherein the read reference current is incrementally increased by adjusting a digital input code to the DAC (244) to incrementally increase the OTP reference voltage.

Description

BACKGROUND OF THE INVENTION Field of the Invention This invention relates in general to a memory and more specifically to a memory with one time programmable (OTP) cells. Background In general, a magneto-resistive random access memory (MRAM) one time programmable (OTP) cell can be created based on creating an antifuse of the magnetic tunnel junction (MTJ) element in the memory cell. This can be achieved by providing a sufficient current through the MTJ to result in a dielectric breakdown of the tunnel dielectric of the MTJ. This results in a blown memory cell which has a low resistance/high current path through the MTJ, as compared to an MTJ which has not experienced a dielectric break down (i.e. a non-blown memory cell). In order to operate as an OTP, though, the dielectric breakdown of the tunnel dielectric should be permanent to maintain its blown state. A hard breakdown tunnel dielectric permanently and reliably maintains its blown state, while a soft breakdown tunnel dielectric may lead to long term reliability issues due to breaking of the high current path which was created with the dielectric breakdown. Therefore, there is a need for improved programming of an OTP memory cell which ensures that the OTP cell is formed with a hard breakdown of the dielectric rather than a soft breakdown in order to achieve improved reliability. US 10 861 524 B1 (ROY ANIRBAN [US] ET AL) describes a MRAM with OTP cells. CN 105 427 888 A (GALLOP CREATION LTD) describes a programming method and programming equipment of anti-fuse type primary programmable memory BRIEF DESCRIPTION OF THE DRAWINGS The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings. FIG. 1. is a diagram of an MRAM according to one embodiment of the present invention.FIG. 2 is a side view of a MRAM cell of FIG. 1 according to one embodiment of the present invention.FIG. 3 is a graph showing a distribution of resistances of cells of an MRAM array according to one embodiment of the present invention.FIG. 4 is a schematic diagram of a reference circuit of the MRAM of FIG. 1, according to one embodiment of the present invention.FIG. 5 is a flow diagram for a self-referencing OTP write operation performed in the MRAM of FIG. 1, according to one embodiment of the present invention. The use of the same reference symbols in different drawings indicates identical items unless otherwise noted. The figures are not necessarily drawn to scale. DETAILED DESCRIPTION The following sets forth a detailed description of a mode for carrying out the invention. The description is intended to be illustrative of the invention and should not be taken to be limiting. As disclosed herein, an MRAM includes an array of MRAM cells that can be utilized as one-time programmable (OTP) cells. An MRAM is arranged in rows (along word lines) and columns (along bit line/source line pairs), in which the intersection of each row (word line) and column (bit line/source line pair) has a corresponding MRAM cell (i.e. memory cell) having a select transistor and a magnetic tunnel junction (MTJ). In one embodiment, all the cells of a memory are configured as OTP devices. In some embodiments, the memory may include both OTP cells as well as reprogrammable memory cells (in which reprogrammable memory cells can be written multiple times over the life of the memory). The MTJs of the cells which are used as OTP devices are "blown" during an OTP write in order to provide a permanent conductive state which is determinable from the conductive state of an unblown cell (i.e. non-blown cell). In this manner, permanent values can be stored in the memory which can later be read. Any OTP cell which is not blown during an OTP write can either be in a high resistive state (HRS) or a low resistive state (LRS). The blown state of an MRAM cell has a relatively low resistance value as compared to the non-blown state, regardless of whether the non-blown cell is in the HRS or the LRS. For an OTP read, a blown state of an MRAM cell may correspond to a permanently stored "0" logic state (while a non-blown state may correspond to a stored "1" logic state, regardless of whether the non-blown state is the HRS or the LRS). Non-blown OTP cells can be reprogrammed with non-OTP writes, as desired, between the HRS and the LRS, in which the HRS and the LRS correspond to non-OTP stored logic states (e.g. a "1" and a "0", respectively). The MTJ of an OTP cell can be blown, during an OTP write operation, by providing a sufficient current through the MTJ to result in a dielectric breakdown of the tunnel dielectric of the MTJ. Ideally, the dielectric breakdown of the dielectric should be permanent to maintain its blown state in order to reliably operate as an OTP. As described above, though, a hard breakdown tunnel dielectric permanently and reliably maintains its blown state, while a soft breakdown tunnel dielect