EP-4439562-B1 - SELF-SELECTING MEMORY DEVICE HAVING POLARITY DEPENDENT THRESHOLD VOLTAGE SHIFT CHARACTERISTICS AND MEMORY APPARATUS INCLUDING THE SAME

Inventors

• YANG, KIYEON
• GU, Dongggeon
• KOO, BONWON
• PARK, JEONGHEE
• SUNG, HAJUN
• AHN, DONGHO
• WUN, Zhe
• LEE, CHANGSEUNG
• CHOI, MINWOO

Dates

Publication Date

20260506

Application Date

20240312

Claims (15)

1. A memory apparatus (200) comprising: a plurality of word planes (WP) extending along a plane defined by a first direction (x) and a second direction (y) and apart from each other in a third direction (z) crossing the first direction and the second direction; a plurality of vertical bit lines (VBL) extending in the third direction and arranged two-dimensionally in the first direction and the second direction; and a plurality of memory cell strings (MCS) surrounding surfaces of the plurality of vertical bit lines and extending in the third direction, wherein the plurality of memory cell strings and the plurality of vertical bit lines are arranged to penetrate the plurality of word planes in the third direction, an area surrounded by one of the plurality of word planes in each of the plurality of memory cell strings corresponds to one memory cell (MC), the memory cell has Ovonic threshold switching characteristics, the memory cell is configured to have a threshold voltage of the memory cell be changed as a density of active traps in the memory cell is changed, the threshold voltage changed according to a polarity and an intensity of a bias voltage applied to the memory cell, and characterized in that an element composition distribution is configured to be maintained constant in the memory cell in response to the threshold voltage of the memory cell being changed.
2. The memory apparatus of claim 1, wherein the memory cell is configured to be in any one of a first state having a first threshold voltage and a second state having a second threshold voltage greater than the first threshold voltage.
3. The memory apparatus of claim 2, wherein the memory cell comprises a first region adjacent to a corresponding vertical bit line of the plurality of vertical bit lines and a second region adjacent to a corresponding word plane of the plurality of word planes.
4. The memory apparatus of claim 3, wherein in response to the memory cell being in the first state, a density of active traps in the second region is greater than a density of active traps in the first region.
5. The memory apparatus of claim 3, wherein in response to the memory cell being in the second state, the density of active traps in the second region is less than the density of active traps in the first region.
6. The memory apparatus of claim 3, wherein the density of active traps in the first region and the density of active traps in the second region in response to the memory cell being in the second state are respectively less than the density of active traps in the first region and the density of active traps in the second region in response to the memory cell being in the first state.
7. The memory apparatus of any of claims 3 to 6, wherein the first region and the second region have a ring shape and are concentrically arranged, and wherein a radial width of the second region is less than a radial width of the first region.
8. The memory apparatus of any of claims 2 to 7, wherein in response to the memory cell being in the first state, the memory cell is configured to be converted into the second state by applying a negative bias voltage to the memory cell.
9. The memory apparatus of claim 8, wherein a pulse width at a peak of the negative bias voltage applied to the memory cell is 0.7 nsec or more and less than 10 nsec.
10. The memory apparatus of any of claims 2 to 7, wherein in response to the memory cell being in the second state, the memory cell is configured to be converted into the first state by applying a positive bias voltage greater than or equal to the second threshold voltage to the memory cell.
11. The memory apparatus of any of claims 2 to 10, wherein the memory apparatus is configured to operate such that in a read operation, a read voltage between the first threshold voltage and the second threshold voltage is applied to the memory cell.
12. The memory apparatus of any preceding claim, wherein the memory cell comprises a single layer comprising at least one material of GeAsSeln, GeAsSeSIn, GeAsSeSbln, GeAsSeTeln, GeAsSeAlln, GeSbSeln, and GeSbSeNIn, and wherein a concentration of indium (In) in the memory cell is 10 at% or less.
13. The memory apparatus of any of claims 3 to 11, wherein the memory cell comprises a single layer comprising GeAsSe, and in the memory cell, an atomic percent of germanium (Ge) is 10 at% or more and 30 at% or less, an atomic percent of arsenic (As) is 10 at% or more and 50 at% or less, and an atomic percent of selenium (Se) is 40 at% or more and 80 at% or less.
14. The memory apparatus of claim 13, wherein in response to the memory cell being changed from the first state to the second state or from the second state to the first state, the memory device is configured such that a ratio of Ge, As, and Se is maintained constant in the first region and the second region of the memory cell.
15. The memory apparatus of claim 13, wherein a difference between a concentration of Se in the first region in response to the memory cell being in the first state and the concentration of Se in the first region in response to the memory cell being in the second state is within 10% of the concentration of Se in the first region in response to the memory cell being in the first state.

Description

FIELD OF THE INVENTION Various example embodiments relate to a self-selecting memory device having polarity dependent threshold voltage shift characteristics and/or to a memory apparatus including the self-selecting memory device. BACKGROUND OF THE INVENTION Along with the miniaturization of electronic products, there is an increasing demand for high-density memory devices. A cross-point memory device has a memory structure in which an upper electrode and a lower electrode are arranged vertically crossing each other and a memory cell is disposed at an intersection area. The structure has a merit of having a small memory cell on a plane. Generally, in order to prevent or reduce the likelihood of a sneak current between neighboring memory cells, a memory cell in a cross-point memory apparatus includes a 2-terminal selector and a memory device, which are connected to each other in series. Therefore, an aspect ratio of a unit memory cell may increase too much so that the manufacturing process of a memory cell is complicated and there is a limitation in increasing the memory capacity of a memory apparatus. Korean Patent Application Number KR 2021 0153275 A describes an electronic device comprising a memory cell in which a chalcogenide film and at least one threshold voltage adjustment film are stacked. SUMMARY OF THE INVENTION Various example embodiments provide a self-selecting memory device having both a selector function and a memory function using polarity dependent threshold voltage shift characteristics and a memory apparatus including the self-selecting memory device. Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of variously described example embodiments. According to some example embodiments, there is provided a memory apparatus according to claim 1. Some embodiments propose self-selecting memory (SSM) using a polarity dependent Vth shift mechanism. Such a SSM can be applied as the cross-point memory device because it has a simple device structure and can simultaneously implement memory and selector functions with a single device, but it can also be applied as a vertical device that can dramatically increase memory capacity. When applied to the vertical device, the hole diameter can be reduced due to the simplicity of the components, which is advantageous for increasing memory density. There is proposed a technology to realize the Self-Selecting Memory by generating a Vth shift using only a change in the trap state without causing migration of components inside the OTS. The OTS is a material that has many trap states inside and generates a threshold switching phenomenon by them. When a negative bias opposite to the first-firing (F.F) driving bias is applied to the OTS, the trap state in the OTS changes from an activated state to a de-activated state, and a Vth shift phenomenon occurs when a positive bias is subsequently applied. By utilizing the Vth shift phenomenon of the OTS material, it is possible to realize a self-selecting memory that has both selector and memory characteristics. Embodiments may provide a self-selecting memory in which Vth shift occurs due to a phenomenon that the trap state changes depending on a polarity of an electric field. Some embodiments may provide a self-selecting memory in which a deep trap is generated/destroyed in a region near electrode/SSM and a Vth shift is generated by changing a polarity of an electric field. Embodiments may provide a device in which a Vth of the SSM changes by forming an interfacial tunneling barrier (ITB) at an interface with the electrode according to a polarity of a bias applied when writing to the GeAsSe-based SSM device. Some embodiments may provide a SSM device utilizing a fact that the Vth increases due to formation of an ITB at the interface with a top electrode when a bias opposite to F.F. is applied after the F.F bias is applied, and the Vth shift occurs due to a polarity of an applied bias. Alternatively or additionally according to various example embodiments, a memory apparatus includes a plurality of bit lines extending in a first direction, a plurality of word lines extending in a second direction crossing the first direction, and a plurality of memory cells at intersections between the plurality of bit lines and the plurality of word lines. The plurality of memory cells each have Ovonic threshold switching characteristics, the plurality of memory cells are each configured to have threshold voltages of the plurality of memory cells each be changed as a density of active traps in the plurality of memory cells is changed, the threshold voltages changed according to a polarity of and an intensity of a bias voltage applied to respective ones of the plurality of memory cells An element composition distribution is configured to be maintained constant in the memory layer in response to the threshold voltage of the memory laye