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EP-4443435-B1 - A VICTIM CACHE THAT SUPPORTS DRAINING WRITE-MISS ENTRIES

EP4443435B1EP 4443435 B1EP4443435 B1EP 4443435B1EP-4443435-B1

Inventors

  • BHORIA, NAVEEN
  • ANDERSON, Timothy, David
  • HIPPLEHEUSER, Pete, Michael

Dates

Publication Date
20260513
Application Date
20200526

Claims (15)

  1. An eviction method, comprising: detecting an idle activity on a processor interface; characterised by in response to detecting the idle activity on the processor interface: draining a write-miss entry, which is stored inside a victim cache (704, 706), from the victim cache (704, 706).
  2. The eviction method of claim 1, wherein: The idle activity is detected when a processor (414, 514) has not issued any commands on the processor interface for N number of clock cycles.
  3. The eviction method of claim 2, wherein: the N number of clock cycles is predetermined, or optionally the N number of clock cycles is configurable.
  4. The eviction method of claim 1, further comprising: looking for write-miss entries in the victim cache (704, 706) by examining the victim cache (704, 706) in an order and draining entries corresponding to write-miss entries.
  5. The eviction method of claim 1, wherein: draining the write-miss entry includes draining the write-miss entries in one of a first in first out, least recently used, or random basis.
  6. The eviction method of claim 1, wherein: the draining of the write-miss entry includes sending an eviction trigger request to a victim cache controller (734) for a selected write buffer cache line of the victim cache (704, 706) associated with the write-miss entry.
  7. The eviction method of claim 6, wherein: in response to receiving the eviction trigger request, the victim cache controller (734) checks if there is an entry on the selected write buffer cache line of the victim cache (704, 706).
  8. The eviction method of claim 1, further comprising: storing the write-miss entry in a drain buffer (716) until the write-miss entry is accepted by a memory.
  9. The eviction method of claim 1, wherein: the draining the write-miss entry from the victim cache (704, 706) is in response to a processor (414, 514) writing out half of the write-miss entry.
  10. A device, comprising: a victim cache (704, 706); and a controller (714) configured to detect an idle activity on a processor interface; wherein in response to detecting the idle activity on the processor interface, the controller (714) is configured to: flush a write-miss entry, which is stored inside the victim cache (704, 706), from the victim cache (704, 706).
  11. The device of claim 10, wherein: the idle activity is detected when a processor (414, 514) has not issued any commands on the processor interface for N number of clock cycles.
  12. The device of claim 11, wherein: the N number of clock cycles is predetermined, or optionally the N number of clock cycles is configurable.
  13. The device of claim 10, wherein: the controller (714) is configured to look for write-miss entries in the victim cache (704, 706) by examining the victim cache (704, 706) in an order and drain entries corresponding to write-miss entries.
  14. The device of claim 10, wherein: the controller (714) is configured to flush the write-miss entry by flushing the write-miss entries in one of a first in first out, least recently used, or random basis.
  15. The device of claim 10, further comprising: a victim cache controller (734), wherein: the victim cache controller (734) is configured to drain the write-miss entry in response to an eviction trigger request for a selected write buffer cache line of the victim cache (704, 706) associated with the write-miss entry, and optionally in response to the eviction trigger request, the victim cache controller (734) is configured to check if there is an entry on the selected write buffer cache line of the victim cache (704, 706).

Description

BACKGROUND In a multi-core coherent system, multiple processor and system components share the same memory resources, such as on-chip and off-chip memories. Memory caches (e.g., caches) may provide an amount of high-speed memory located operationally near (e.g., close to) a processor, as compared to main memory. In general, the more a cache is operationally nearer to a processor, the lower the latency, i.e., fewer processor clock cycles are used to fulfill a memory request. Generally, the cache memory closest to a processor includes a level 1 (L1) cache that is often directly on a die with the processor. Many processors also include a larger level 2 (L2) cache. This L2 cache is generally slower than the L1 cache but may still be on the die with the processor cores. The L2 cache may be a per processor core cache or shared across multiple cores. Often, a larger, slower L3 cache, either on die, as a separate component, or another portion of a system on a chip (SoC) is also available to the processor cores. Memory systems such as caches can be susceptible to data corruption, for example, due to electronic or magnetic interference from cosmic rays, solar particles, or malicious memory accesses. As processors are increasingly used in critical and/or other fault-intolerant systems, such as self-driving vehicles and autonomous systems, techniques to protect memory systems from data corruption are increasingly being applied to the memory systems. One such technique is the use of error correcting codes (ECC) to detect and correct memory corruption. Implementing ECC in high speed cache memory is challenging as ECC can introduce additional timing overhead that needs to be accounted for. For example, a high speed cache memory system may have a five stage memory pipeline for determining whether a memory address being accessed is in the cache and retrieving the contents of the cache memory. Each stage may take one clock cycle, which at 1 GHz, is about one nanosecond. Error checking the contents of the cache memory can substantially take up a full clock cycle. What is needed are techniques for increasing cache performance for fault tolerant caches. US 2015/067259 A1 discloses that when a core is to be placed into a certain low power state, potentially its Last Level Cache (LLC) slice can be flushed. Moreover, when the idle cache slice is powered on and made available to a non-idle processing core, it may be used as a victim cache. SUMMARY The invention is set out in the appended set of claims. The dependent claims set out particular embodiments. This description relates to a caching system. More particularly, but not by way of limitation, aspects of this description relate to a caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes a set of cache lines, line type bits configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data, and an eviction controller configured to flush stored write-miss data based on the line type bits. Another aspect of this description relates to a method for caching data including receiving, by a caching system, a write memory request for a memory address, determining, by a first sub-cache of the caching system, that the memory address is not cached in the first sub-cache, determining, by second sub-cache of the caching system, that the memory address is not cached in the second sub-cache, storing data associated with the write memory request in the second sub-cache, storing, in a line type bit of the second sub-cache, an indication that the stored data corresponds to a write-miss, and flushing the stored data based on the indication. Another aspect of this description relates to a device including a first sub-cache, and a second sub-cache in parallel with the first sub-cache; wherein the second sub-cache includes a set of cache lines, line type bits configured store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data, and an eviction controller configured to flush stored write-miss data based on the line type bits. Another aspect of this description relate to a caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes: a set of cache lines, line type bits configured to store an indication that a corresponding line of the set of cache lines is configured to store write-miss data, and an eviction controller configured to evict a cache line of the second sub-cache storing write-miss data based on an indication that the cache line has been fully written. Another aspect of this description relates to a method for caching data, including receiving, by a caching system, a write memory request for a memory address, determining, by a first sub-cache of the caching system, that the memory address is not cached i