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EP-4453707-B1 - MANAGING OPERATIONS IN MEMORY SYSTEMS

EP4453707B1EP 4453707 B1EP4453707 B1EP 4453707B1EP-4453707-B1

Inventors

  • LIU, WEILIN

Dates

Publication Date
20260506
Application Date
20230307

Claims (14)

  1. A system (102) comprising: a memory device (104, 304, 502); and a controller (106, 306, 406), wherein: the controller (106, 306, 406) is configured to: while performing data transfer to the memory device (104, 304, 502) for a first operation corresponding to a first command, check whether a second command is received, wherein performing the data transfer to the memory device (104, 304, 502) comprises transferring a plurality of allocation units (AU), wherein each allocation unit (AU) has a size that is smaller than a size of a page, wherein the current allocation unit (AU) is not a last allocation unit (AU) of the plurality of allocation units (AU) of data; in response to determining that the second command is received and that data transfer in a current allocation unit is completed, send a suspend command to the memory device (104, 304, 502); and in response to determining that the second command is received and that the data transfer in the current allocation unit is not completed, wait for the data transfer in the current allocation unit to be completed; and the memory device (104, 304, 502) is configured to: in response to receiving the suspend command from the controller (106, 306, 406), suspend data reception for the first operation; allocate a buffer space for a second operation corresponding to the second command; perform the second operation using the buffer space allocated for the second operation; and return an execution result of the second operation to the controller (106, 306, 406), wherein the buffer space allocated for the second operation is different from that allocated for the first operation.
  2. The system of claim 1, wherein the controller (106, 306, 406) is configured to: repeatedly check whether the second command is received while performing the data transfer to the memory device (104, 304, 502) for the first operation.
  3. The system (102) of any one of the preceding claims, wherein each allocation unit has a size that is equal to one fourth of a page size.
  4. The system (102) of any one of the preceding claims, wherein the controller (106, 306, 406) is configured to: in response to receiving the execution result of the second operation from the memory device (104, 304, 502), send a resume command to the memory device (104, 304, 502) to resume the first operation; and wherein the memory device (104, 304, 502) is configured to: in response to receiving the resume command from the controller (106, 306, 406), continue the data reception for the first operation.
  5. The system (102) of claim 4 wherein the memory device (104, 304, 502) is further configured to: in response to receiving the resume command from the controller (106, 306, 406), restore context of the first operation from a first buffer space.
  6. The system (102) of any one of the preceding claims, wherein the controller (106, 306, 406) is further configured to: in response to receiving the execution result of the second operation from the memory device (104, 304, 502), send an abort command to the memory device (104, 304, 502) to abort the first operation; and wherein the memory device (104, 304, 502) is configured to: in response to receiving the abort command from the controller (106, 306, 406), release the first buffer space that has previously been allocated for the first operation, wherein the first buffer space is different from the buffer space allocated for the second operation.
  7. The system (102) of any one of preceding claims, wherein the controller (106, 306, 406) is configured to: in response to completing the second operation, release the buffer space allocated for the second operation.
  8. The system (102) of any one of preceding claims, wherein the operations comprise: in response to receiving the execution result of the second operation from the memory device, sending an abort command to the memory device to abort the first operation.
  9. A method performed by a system according to claim 1, wherein the method comprises: while performing data transfer to the memory device (104, 304, 502) for a first operation corresponding to a first command, checking, by the controller (106, 306, 406), whether a second command is received, wherein performing the data transfer to the memory device (104, 304, 502) comprises transferring a plurality of allocation units (AU), wherein each allocation unit (AU) has a size that is smaller than a size of a page, wherein the current allocation unit (AU) is not a last allocation unit (AU) of the plurality of allocation units (AU) of data; in response to determining that the second command is received and that data transfer in a current allocation unit is completed, sending, by the controller (106, 306, 406), a suspend command to the memory device (104, 304, 502); in response to receiving the suspend command from the controller (106, 306, 406), suspending, by the memory device (104, 304, 502), data reception for the first operation; allocating, by the memory device (104, 304, 502), a buffer space for a second operation corresponding to the second command; performing, by the memory device (104, 304, 502), the second operation using the buffer space allocated for the second operation; returning, by the memory device (104, 304, 502), an execution result of the second operation to the controller (106, 306, 406), wherein the buffer space allocated for the second operation is different from that allocated for the first operation; receive a command (CMD) and/or a control signal (CTRL) by one or more processing cores of a microcontroller unit (MCU) (510), through an input/output buffer of the memory device (104, 304, 502); and control overall operation of the memory device (104, 304, 502) by one or more processing cores of the microcontroller unit (510) in response to the command (CMD) and/or the control signal CTRL.
  10. The method of claim 9, further comprising: in response to determining that the second command is received and that the data transfer in the current allocation unit is not completed, waiting for the data transfer in the current allocation unit to be completed and repeatedly checking whether the second command is received while performing the data transfer to the memory device (104, 304, 502) for the first operation.
  11. The method of any one of claims 9-10 further comprising: in response to receiving the execution result of the second operation from the memory device (104, 304, 502), sending, by the controller (106, 306, 406), a resume command to the memory device (104, 304, 502) to resume the first operation; and in response to receiving the resume command from the controller (106, 306, 406), continuing, by the memory device (104, 304, 502), the data reception for the first operation.
  12. The method according to claim 11 further comprising: in response to receiving the resume command from the controller (106, 306, 406), restoring context of the first operation from a first buffer space.
  13. The method of any one of claims 9-12, further comprising: in response to receiving the execution result of the second operation from the memory device (104, 304, 502), sending, by the controller (106, 306, 406), an abort command to the memory device (104, 304, 502) to abort the first operation; and in response to receiving the abort command from the controller (106, 306, 406), releasing, by the memory device (104, 304, 502), a first buffer space that has previously been allocated for the first operation, wherein the first buffer space is different from the buffer space allocated for the second operation;
  14. The method of any one of claims 9-13, further comprising: in response to completing the second operation, releasing the buffer space allocated for the second operation.

Description

TECHNICAL FIELD The present disclosure generally relates to a memory system, and more specifically, to management of suspend and resume operations of a memory system. BACKGROUND A memory system can include one or more memory components that store data. The memory components can be, for example, non-volatile memory components and volatile memory components. In general, a host system can utilize a memory system to store data in the memory components and retrieve data from the memory components. The US 2019/087101A1 describes a memory system with a controller that is configured to control a transfer phase. The US 2021/142855A1 describes a memory device performing a data program operation or a data erase operation. The US 2022/171571A1 describes a memory system that suspends execution of a first command when receiving a lock request from the host, and resumes the execution. The US 2018/157498A1 describes how background processes are adjusted in their priority such that foreground processes are not always blocking the executation of the background processes. SUMMARY The present disclosure describes management of suspend and resume operations in a memory system. In one aspect, for example, the present disclosure describes a system according to claim 1. In still another aspect, the present disclosure describes a method according to claim 9. The details of one or more implementations of the subject matter of this disclosure are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates a block diagram of an example system having a memory device, in accordance with some aspects of the present disclosure.FIG. 2A illustrates a diagram of an example memory card having a memory device, in accordance with some aspects of the present disclosure.FIG. 2B illustrates a diagram of an example solid-state drive (SSD) having a memory device, in accordance with some aspects of the present disclosure.FIG. 3 illustrates a block diagram of an example memory system, in accordance with some aspects of the present disclosure.FIG. 4 illustrates a block diagram of an example memory controller, in accordance with some aspects of the present disclosure.FIG. 5 illustrates a schematic diagram of an example memory device, in accordance with some aspects of the present disclosure.FIG. 6 illustrates an example graph of managing suspend and resume operations associated with a memory system, in accordance with some aspects of the present disclosure.FIG. 7 illustrates another example graph of managing suspend and resume operations associated with a memory system, in accordance with some aspects of the present disclosure.FIG. 8 is a swimlane diagram of an example process performed by a memory controller and a memory device, in accordance with some aspects of the present disclosure.FIG. 9 is a flowchart of an example process performed by a memory controller, in accordance with some aspects of the present disclosure.FIG. 10 is a flowchart of an example process performed by a memory device, in accordance with some aspects of the present disclosure. Like reference numbers and designations in the various drawings indicate like elements. DETAILED DESCRIPTION A memory system can be a storage device, a memory module, or a hybrid of a storage device and memory module. Examples of storage devices and memory modules are described below in conjunction with FIG. 1 and FIGS. 2A and 2B. In general, a host system can utilize a memory system that includes one or more memory components, such as memory devices that store data. The host system can provide data to be stored in the memory device and can request data to be retrieved from the memory device. A memory device can include multiple memory cells. Each memory cell can be configured with a different storage mode or state such as a single-level cell (SLC) or a multi-level cell (MLC). The SLC can store only one bit per memory element, whereas the MLC is capable of storing more than a single bit of information. For example, a triple level cell (TLC) is capable of storing three bits of data, a quadruple level cell (QLC) is capable of storing four its of data, and a penta level cell (PLC) is capable of storing five bits of data. TLC, QLC, PLC, and other cells capable of storing more than a single bit of information are collectively referred to as MLC in this specification. The state of the memory cell can be programmed, and the state of the memory cell can be determined by comparing a read voltage of the memory cell against one or more read level thresholds. QoS (quality of service) is a key evaluation factor for memory systems. QoS metrics can include, for example, latency/response time, system throughput, and other measurements. Different QoS latency metrics or numbers can be established for various applications. For example