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EP-4456518-B1 - PHYSICAL LAYER ENTITY AND METHOD FOR MANAGING PACKET HEADER FIELDS

EP4456518B1EP 4456518 B1EP4456518 B1EP 4456518B1EP-4456518-B1

Inventors

  • KUNCHAPU, NAGESWARA RAO
  • MEHTA, KRUPAL JITENDRA
  • BARIMAR, Ashwini Kumari
  • BHARADWAJ, PRAVEEN S

Dates

Publication Date
20260506
Application Date
20230724

Claims (11)

  1. A method for managing packet header fields in a physical, hereinafter referred to as PHY, layer (100), comprising: receiving, by a header descriptor array, hereinafter referred to as HDA (102), of a PHY layer (100), a data packet and a status signal of the data packet, the status signal being produced by a header cyclic redundancy check; writing, by the HDA (102), a header field for the received data packet in a storage element array (202); storing, by the HDA (102), the written header field and the status signal of the data packet in a header field array (106); and fetching, by the HDA (102), the header field of the data packet by enabling parallel reading of a plurality of locations of the header field array (106); wherein the writing of the header field is performed using a write interface module (104) of the HDA (102). wherein the write interface module (104) comprises said storage element array (202) and a combinational logic (204) for writing and updating a plurality of header fields by a plurality of internal blocks of the PHY layer (100), wherein updating a same header field by the plurality of internal blocks at the same time includes updating the same header field based on priority; and wherein the write interface module (104) is configured to track the received status signal to verify if the received data packet is good or bad wherein the verification is performed before writing the header field, a received packet being considered good if the header cyclic redundancy check of the packet is not corrupted and bad otherwise.
  2. The method as claimed in claim 1, wherein at least one re-transmission request is received for the data packet.
  3. The method as claimed in any preceding claim, wherein the HDA (102) comprises a plurality of read interface modules (108), wherein each read interface module (108) comprises a multiplexer (402), an AND gate (404) and a programmable delay element for enabling the parallel reading of the header field array (106).
  4. The method as claimed in any preceding claim , wherein the status signal of the data packet is generated by an internal block of the PHY layer (100).
  5. The method as claimed in any preceding claim, wherein the transmission and re-transmission of the data packet is done with an ultra-low packet error rate.
  6. A physical, hereinafter referred to as PHY, layer (100) comprising: a header descriptor array, hereinafter referred to as HDA (102) configured to: receive a data packet and a status signal of the data packet, the status signal being produced by a header cyclic redundancy check; write a header field for the received data packet in a storage element array (202); store the written header field and the status signal of the data packet in a header field array (106); and fetch the header field of the data packet by enabling parallel reading of a plurality of locations of the header field array (106), wherein the HDA (102) comprises a write interface module (104) for writing the header field; wherein the write interface module (104) comprises said storage element array (202) and a combinational logic (204) for writing and updating a plurality of header fields by a plurality of internal blocks of the PHY layer (100), wherein updating a same header field by the plurality of internal blocks at the same time includes updating the same header field based on a priority; and wherein the write interface module (104) is configured to track the received status signal to verify if the received data packet is good or bad wherein the verification is performed before writing the header field, a received packet being considered good if the header cyclic redundancy check of the packet is not corrupted and bad otherwise.
  7. The PHY layer as claimed in claim 6, wherein at least one re-transmission request is received for the data packet.
  8. The PHY layer (100) as claimed in claim 6 or 7, wherein the HDA (102) comprises a plurality of read interface modules (108), wherein each read interface module (108) comprises a multiplexer, an AND gate and a programmable delay element for enabling the parallel reading of the header field array (106).
  9. The PHY layer (100) as claimed in any of claims 6 to 8, wherein the status signal of the data packet is generated by an internal block of the PHY layer (100).
  10. The PHY layer (100) as claimed in any of claims 6 to 9, wherein the transmission and re-transmission of the data packet is done with an ultra-low packet error rate.
  11. The method as claimed in claim 1, wherein the write interface module (104) is configured to track the received status signal to verify if the data packet is missing.

Description

TECHNICAL FIELD Embodiments of the inventive concept disclosed herein relate to a physical (PHY) layer and methods for managing packet header fields in a physical (PHY) layer. DISCUSSION OF RELATED ART In general, packet data networks are constructed based on multi-layer communication models, which consist of a physical (PHY) layer for encoding and decoding data into signals and transmitting them over a physical medium. The PHY layer is capable of transferring high-speed data between electronic components, such as between sensors, cameras, display units, and their corresponding electronic control units (ECUs). Additionally, the multi-layer communication model includes a data link layer that ensures reliable transmission of data over a network, while also interfacing with the PHY layer and a network layer. After encoding and decoding received data, the data packets may contain errors, and a packet error rate (PER) defines the likelihood of errors occurring in the decoded data. For example, in the automotive industry, short burst noises can arise due to factors that could disrupt the transmission of data packets between the electronic components. Therefore, to minimize errors and attain a low PER, packet data networks utilize one or more error detection and/or error correction capabilities within both the PHY layer and the data link layer. Traditionally, the data packets are processed in the data link layer by the utilization of queues, First-In-First-Out queues (FIFOs), and other similar mechanisms. Each data packet can be individually examined and then processed using a re-transmission mechanism. For example, if a data packet becomes corrupted due to short burst noises, a queuing method may be employed to request the re-transmission of the data packet. However, this serial way of implementation may take a considerable amount of time to execute multiple error corrective actions. US 2019/0306287 A1 describes a low-latency pipeline for media-to-ethernet frame packaging. SUMMARY The invention provides a method for managing packet header fields in a physical (PHY) layer, and to a physical (PHY) layer according to the appended independent claims. Preferred embodiments are covered by the appended dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS Embodiments of the inventive concept disclosed herein are illustrated in the accompanying drawings in which like reference letters or numerals indicate corresponding parts. The embodiments disclosed herein will be better understood from the following description with reference to the drawings, in which: FIG. 1 depicts a physical (PHY) layer for managing packet header fields, according to embodiments as disclosed herein;FIG. 2 depicts a write interface module of a header descriptor array (HDA), according to embodiments as disclosed herein;FIG. 3 depicts a timing diagram of the write interface module, according to embodiments as disclosed herein;FIG. 4 depicts a read interface module of the HDA, according to embodiments as disclosed herein;FIG. 5 depicts a timing diagram of the read interface module, according to embodiments as disclosed herein;FIG. 6 depicts a detailed block diagram of the HDA of the PHY layer, according to embodiments as disclosed herein; andFIG. 7 depicts a method for managing packet header fields in a PHY layer, according to embodiments as disclosed herein. DETAILED DESCRIPTION OF THE EMBODIMENTS The embodiments of the inventive concept disclosed herein and the various features thereof are explained more fully with reference to the accompanying drawings in the following detailed description. Descriptions of well-known components and processing techniques are omitted. The embodiments described herein are intended to facilitate an understanding of ways in which the inventive concept may be practiced. Accordingly, the disclosed embodiments should not be construed as limiting the scope of the inventive concept. The embodiments disclosed herein provide a physical (PHY) layer that stores and accesses header fields of one or more data packets, thus supporting an ultra-low Packet Error Rate (PER) while maintaining low latency. FIG. 1 depicts a PHY layer 100 for managing packet header fields. The PHY layer 100 comprises a header descriptor array (HDA) 102. The HDA 102 is a centralized module for storing and accessing one or more data packet header fields. In other words, the HDA 102 stores and accesses header fields of one or more data packets. The HDA 102 can receive at least one data packet and at least one status signal of the data packet. The HDA 102 stores at least one header field, a plurality of internally generated fields, and the status signal of the data packets. The HDA 102 can store complete header fields of any data packet, wherein each data packet can be forwarded in a regular order to a data link layer, while also enabling the processing of re-transmission requests to the data link layer. The HDA 102 can further track the status of the plurality